I want to simulate openMSP430 core in ModelSim where actually i could not find "stimulus.v" file and got an error "can't find stimulus.v file in tb_openMS430". Kindly help me

This has been asked and answered previously:

https://groups.google.com/forum/#!topic/discuss_openmsp430/mIZjPMyPKoE

The general topic is "How to run programs on Modelsim" and it is generic to MSP430 or Angel ARM, or MIPS or other microcontrollers, etc, etc.

In general, if you wish to provide stimulus to a design, then you should examine the needed input to that design.

As a corollary, you should also capture the expected output for that given input. You could call this a "testbench" if you had all the inputs and outputs for the MSP430 as it was executing your "stimulus.v"

I hope that helps you, good luck.

You can find the stimulus.v by enabling toolbar option.

Afterthat you can see the toolbar in left side of the project.

Hello, Can somebody please tell me about "instruction pipeline" in openmsp430 core i.e how many pipeline stages it has and how it works??

Ummmmmm... You could just download the source and answer the question yourself...

I read all the docs provided in the the project but could not find any material related to pipeline or anything related to internal structure of CPU.Kindly refer me to any relevant site or doc if possible.
Thanks

Hi Umer,

The openMSP430 implements a completely standard "Fetch-Decode-Execute" pipeline.

I have attached a small commented waveform snapshot hopefully illustrating that.

Cheers,
Olivier

Hi Olivier,

im trying to understand the Pipeline more deeply.
Does the Pipeline also have something like an bypass or is it always stalled until the last execution was completely finished?
What are the Pipeline registers (simply all clocked regs in frontend.v)?

Thanks in advance,

Felix

Hi Felix,

The pipeline of the openMSP430 has no bypass and will always be stalled until completion of the current execution stage.
As there is only a single execution unit, it is not possible to speed that up.

The FETCH stage registers are the program memory registered output.
The DECODE stage registers are located in the omsp_frontend.v file in the "// 6) DECODE INSTRUCTION" section (line 515).
The EXECUTION stage registers are different depending on the kind of instruction currently executing (could be a Rx register, a data memorz word, ...).

I hope this helps,
Olivier

Hi Oliver,

I am unable to download and extract the tar file from the overview page as it shows below error:

gzip: stdin: unexpected end of file
tar: Unexpected EOF in archive
tar: Unexpected EOF in archive
tar: Error is not recoverable: exiting now

I have tried the svn command also. That's also failing after downloading some docs.

Kindly help me with a workaround for this as I am looking forward working with this for my Masters' project.




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Thanks & Regards,
Ammu

Hello,

You can download the archive here: http://opencores.org/download,openmsp430

After downloading; run: tar -zxvf openmsp430_latest.tar.gz

Greets,
Sander

Hi,

if it still doesn't work from OpenCores, you can try out to download from GitHub:

https://github.com/olgirard/openmsp430/archive/master.zip

Oliv'

Zip file worked! Thank you so much!

Regards,
Ammu

.tar file is still not working. But zip file worked. Thank you so much for your reply!

Regards,
Ammu