



Cycles in a design
by Unknown on Apr 10, 2005 |
Not available! | ||
Hi,
I am using Xilinx ISE 7.1i to run a design in Verilig for power consumption. I am using ModelSim simulator. I need to find out the number of cycles for which my design runs i.e the number of cycles that the design takes. How can I do this. Will ISE or ModelSim give me an estimate of this or do i have to use any other tool Thanks, Arvind |



