I have a small amount of FPGA experience, and I've gotten quite interested in software defined radio. An important component in software radio is a digital up/down converter (DDC/DUC) to decimate/interpolate a discrete time signal.

I have very little experience in SOC design so I have a question. Does it make sense to design a DDC/DUC as an SOC peripheral? Does it make sense to make this device wishbone compatible? I haven't found such a core anywhere in the projects, is there a reason (other than that no one has decided to do it) for this? Would OpenCores benefit from the addition of this core?

The plan would be to create the DDC, the input of which would be connected by the user (I don't think it makes sense for this to be through the wishbone bus?) to the output of the controller for the Analog-To-Digital converter, and the output of the DDC would be connected either by the user to other DSP cores, or directly to the Wishbone bus where the output would be written to memory or transferred through DMA do some other device. Does this make sense? Can anyone offer some suggested reading?

What you say isn't entirely true... :-) The parts for both a DDC (and probably a DUC) can be found in the Projects, I think... There's no wrapped up IP, in my experience, because a DDC/DUC often doesn't generalize well enough to package up cleanly as a "core"...

There is a CIC decimation filter... Last time I looked, there were several CORDIC implementations... I think most folks would tend to avoid trying to instantiate a bus in the middle of a downconversion/upconversion processing pipeline... YMMV based on required IF bandwidth...

It might be instructive for you to look at what others have done WRT publically available DDC/DUC implementations... Offhand, the USRP Verilog source is available... I'll try to remember other possible Open Source examples of DDC/DUC implementations...

Best Regards,

/jw

Thanks for the feedback.