Hi All,
I was assigned a project to implement AES3 or AES EBU specification. I managed the code after many internet searches and self ingenuity but finally what I am observing is that I am not able to implement the negative voltage on the real world pins.
In another way it is like when I observe the FPGA ( I am using Xilinx Zynq) pins on an oscilloscope the wave form always operates above the 0V x-axis. However a real working AES3 data line changes both above and below the 0V x-axis.
Do I need an external voltage source to implement negative voltage on the pins?

I am going to assume this is a serious question.

Most digital logic, which includes all Xilinx chips that I know about, use binary states to correspond to binary values. If the signal voltage is near the reference ground voltage, then the signal voltage is zero and it represents a zero. If the signal voltage is nearer the operating voltage (+2.7V for example) relative to ground, then the signal represents a one. The reference ground is arbitrarily designated as 0V. Correctly operating digital logic will present either zero volts or VSS volts on all data lines.

If you get a negative voltage on one of these pins, then you have a power supply problem and you will need to replace your FPGA because it has been damaged.

In the analog data transmission world, signals are commonly transmitted using differential signaling. When this is used, there are two transmission lines, and the difference between their voltages indicates the value of a transmitted bit. When Tx1 is high and Tx2 is low, you have a 1. When Tx2 is high and Tx1 is low, you get a zero. If you connect the ground of an oscilloscope to Tx1 and the probe to Tx2, the signals will appear to fluctuate between -5v and +5v (or whatever your signal voltage is) even though they are probably both always positive relative to board ground.

One caution: Unless you are using a very primitive transmission protocol, your differential signals are probably being modulated so that each distinct state of the signal represents more than one bit. Do not try to validate your AES logic against the transmission signals unless you are sure that your modulation delivers only one bit per state.