I have a microprocessor core (Plasma) and a number of other cores
which i want to connect with the Plasma core sharing address and data
lines together, as the data lines will be driven by multiple drivers(only
one at a time) I wonder what is the proper way of implementing this in
FPGA. Two ways i have in my mind is (1) to use a daisy chain kind of
connection and connect the cores one-at-back-of-other kind of fassion
(2) to make a shared bus using tristate logic. Anyone having experience
in this regard may please suggest something to me.

PS: Sorry if this sounds as a very basic problem, I happen to be a
freshman in I.T. and doing this as a part of my hobby project hence i
dont have much experience in this regard.

On Monday 11 April 2005 01:15 am, ankit.raizada at gmail.com wrote:

You can look at the WISHBONE spec as it gives you a few ideas on how to
connect single MASTER multiple SLAVE and also multi MASTER multi SLAVE
configurations..

You may need to use an arbiter of some sort.. It may be more suitable to use a
huge Mux to direct the traffic... There are speed/size trade-offs between
this and the tristate method.. And also, it's dependent on the features
available in the target technology you're using..

If you look at some SoC examples at opencores, you'll see that it's mostly
done with muxes.. and you can have seperate Input and Output busses..

cheers..

--
with metta,
Shawn Tan