Hi all


My goal is to create a serializer.
To reduce the number of conductors in a backplane, I want to go from parallel signals to serial. In the same stream of data, I also want to extract out the clock. Want to achieve a minimum 100Mbs in the actual data (ie no payload).
I will use a FPGA with SERDES channels with LVDSL drivers.
Unfortunately, I'm quite a novice on the FPGA. A 8B / 10B encoder I found here. But for the clock recovery, I haven't found anything.
Taking the help of you, in search of wisdom.
How do you create the block for clock recovery, the PLL set up? Realize that there are different solutions depending on the manufacture of the FPGA.

Brg

Hi,
You have a number of choices:
1) You oversample the incoming signal, detect flanks and align to them. This solution requires nothing else than logic (and a high-speed clock).
2) You use a SERDES block sometimes present in the IO-blocks in the FPGA.
3) You use a tranceiver block sometimes present in an FPGA.
4) You use a PLL to move the phase of a reference clock. Then you compare the different phases and match them to the flanks of the inbound signal. You then choose the phase which is most in line with the flank of the inbound signal.

Good luck,
Magnus.