Trying to implement a single neuron with various multipliers and compare the processing speed. How can we compute the speed. Iam using Xilinx ISE. Can anyone tell me what type of multiplication algorithm does the "x" symbol (arith lib) implement?

Hi,
I don't have experience with Xilinx, but in Altera there is an option in reports where you can obtain performance after you have compiled your design. For every circuit generated you can then compare the performance reports.
About your NN algorithm question I would need some more information (what algorithm you are using; and the arith lib, is it a specific xilinx library?)

We are implementing single neuron in FPGA without any learning process.So there is no learning algorithm involved.Our aim is two use two different multipliers(standard and Indian vedic) and compare the processing speed of neuron.I have implemented the neuron with standard multiplication.Does the standard multiplication in xilinx follow the Booth multiplication??

There are two instances involved which can possibly decide how the multiplication is done.

The first one ist the source language's interpretation of the multiplication symbol (because
I assume that you have formulated the multiplication as, e.g., a * b). You don't tell us
which language you use. As far as I know, neither Verilog nor VHDL prescribe any algorithm
for multiplication.

The second one is the synthesizer you use to create a bitstring for you FPGA. Its behavior
is of course even less specified than that of the source language. So you can not even be
sure that your multiplier is synthesized the same way in the next version of the synthesizer.
That said, it can be guessed that the synthesizer uses hardware multipliers whenever possible,
i.e., the multiplication is done in parallel (one clock cycle), if the bit width allows this.

So you must either specify your multiplication more explicitly (write a real circuit instead
of the multiplication symbol), or you must look at the output of your synthesizer (Xilinx
has a viewer for the register-transfer representation of the generated circuit).

Hellwig

Thanks for your reply. Iam using VHDL for coding. Well as u said I am using a*b and it is using a single clock cycle and I checked with the RTL circuit that's being generated. It just shows a multiplier and a buffer(attachment of RTL sch). Still not clear how in a single clock cycle multiplication is carried out.

To get an answer for your "how is the * operator synthesized", you must specify:
- Toolset (Xilinx ISE version)
- Target FPGA
- Synthesis Constraints
- Map Constraints

Depending on the operands size, your multiplication will use a DSP macro block. Read on the FPGA distributed DSP resources on your device, to gain insight on which operations you can have with a DSP block, and how can you direct synthesis inference from high-level descriptions.

The image you attached has illegible labels, and does not look like the RTL viewer from ISE.

Regarding the question "How can multiplication be carried out in a single clock cycle?":

The result of a multiplication is a bit vector in which each bit can be expressed as a
boolean function of the bits of both input vectors. It can therefore be realized as a
two-stage and/or combinational circuit. This is at least true for small input vectors.
If the bit width of the operands exceed a certain threshold, multiplication circuits have
to be cascaded. Even then they can compute the answer in a single clock cycle, although
propagation delay will limit the operating frequency.

If the widths of the operands are even bigger, you have to use some sort of sequential
algorithm. Then of course you don't get the answer within a single clock cycle.

Hellwig

Ive coded the booth multiplier in place of "x". But still I ve some issues.
1. If I synchronize the adder with clock, then after synthesis the report shows
"no combinational delay path found". but if theres no clock, then theres some delay in ns.
2. If I have to compare a single neuron with two different multipliers with respect to their speed, then how can I do with synchronization.
3. Iam using presently a very old version of Xilinx ISE6.1i with inbuilt synthesis tool.My target is Spartan 2s family.
4. Lastly I just wanted to know whether I can use the latest Xilinx tool evaluation version for this work, as I am not sure about the limitations of evaluation version.

about your adder code:
1. remove X and Y signals from sensivity list, only clock and reset should be on sensivity list.
2. another issue is double buffering of the addition result. Either: remove SUM and CARRY from the process, and do the assignment to them outside of the process; or: move the result signal declaration to the process body and change it to be a variable.