OpenCores

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Need core using RAM memories and JTAG controlled by khachatur.armenyan on Oct 31, 2014			khachatur.armenyan Posts: 1 Joined: May 3, 2012 Last seen: Oct 31, 2014
I am looking for a core to insert BIST logic in there. For that I need the core to use some memories and jtap tap assess for debug. Any suggestion what design can serve this purpose? Preferably I would like this to be verilog. I am looking for a core to insert BIST logic in there. For that I need the core to use some memories and jtap tap assess for debug. Any suggestion what design can serve this purpose? Preferably I would like this to be verilog.

1/1

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