Dear Friends,
I am new in the subject (using OpenCore IPs), I want to add a new core in "Xilinx Core Generator".
What is the method, is there any user guide for, I have checked the OpenCore web site but there is no description.
What about other IDE environments, like ALTERA QUARTUS II software?
I have attached an OpenCore on FIR filter as a case study.

Help me please?

I'm not sure, but I would have thought that the "Xilinx Core Generator" was about "Xilinx" owned and proprietary cores ...? That said, isn't there a way to package a core from the ISE menu?

My understanding is that there is no way you can put your own IP into ISE CoreGen (which is the previous genration tool). The current Vivado tool supports such a flow with the IP Integrator. Checkout the following document fom Xilnx

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug939-vivado-designing-with-ip-tutorial.pdf

I do also think there is no way to put your own IP CORES to the ISE core generator. so just use it as a module, to instant it where you want to use.

If you have done any RTL design, it is trivial to add custom IP blocks and create a top-level design. Why would you want the s/w to do everything for you?

Hello,
I am new to xilinx core generator so can i get some information how to generate it and how to simulate it.

This is really the wrong forum to ask for help in how to use Xilinx's software. This is the OpenCores forum. While both Xilinx's core generator and OpenCores will both provide you with IP cores that you can use within an FPGA, legally the two are very different. Xilinx cores are proprietary. The license that I have signed when using them states that I will only use them with Xilinx FPGA's. The OpenCores on this web site are different. They have all be released under a public license, and they are (often) written in a way that will allow you to place them on any FPGA--whether that be a Xilinx or an Altera FPGA.

However, out of the kindness of my heart, I was able to Google the Xilinx Core Generator's support documentation here. If you wish to ask questions about how to use it, Xilinx has a paid staff monitoring their forums that will answer your technical questions.

Hope this helps,

Dan

Hello! I am trying to use the i2s_interface with Xilinx ISE Design Suite.
When i try to locate the project file with ISE it finds nothing. If i just try to open the VHDL folder manually there are a bunch of VHDL files. The plan is just to take the project file and do component instantiation into my project. Any ideas?

You may need to think about what a "core" is: it is a piece of an FPGA design. Most "cores" are not complete FPGA designs, and many of the cores on this website are not unique to either Xilinx, Altera, or any other vendor. For these reasons, I would not expect a Xilinx design file with every core directory.

As for the i2s_interface core you mention, it can be configured in multiple different ways. How you wish to configure it, and what you wish to do with it, will determine how you integrate it into your own design. In particular, what you want to do with it will determine which of those VHDL files you want and need and which you don't.

Were I you, I would start with the i2s_interface documentation.

Yours,

Dan

Thank you! Yes i was able to load the VHDL files thru ISE core generator. I used core generator: "CORE Generate UI launched successfully. Use Project -> Add Source to add any cores you create to your Project."
I was also able to open them in word pad. Yes i think i have to choose the module/s i need for the project.

The plan is to receive ADC signal on the FPGA into 16 i2S receivers and send the data thru Ethernet to a PC.

I do use Spartan 6 Nexys3 board it's old. Vivado with newer board will be evaluated also for this project.

Hello! I am studying the code for I2S_interface for use in a project.

I am receiving I2S-data asynchronous into 16-I2S receivers. In the I2S_interface project a dual port ram is used for buffering of I2S data and WISHBONE is used for transferring data between different cores.

My understanding is that dpram works similar to a FIFO but some of the behaviors are different, FIFO has queue first in/first out, memory can fetch data from specific address locations. Is that about correct?

Do any of you have any experience for synchronization of data from the 16 dpram modules before they are sent to an Ethernet module?
The data will be sent thru WISHBONE and then into Ethernet module who receives 32x24 bit of data.

My thoughts are either try to synchronize data at dpram or at WISHBONE by using an arbiter/controller.

Thank you for any ideas and inputs:)