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Operations within a vector
by Unknown on Apr 20, 2005 |
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A VHDL how-would-you-do-this question (if allowed here).
Suppose you have a parametric generation of instances of a certain
component.
Something like:
inst_generator: for i in 0 to PARAMETER generate
my_inst: component_name
port map(
a => a(i), -- an in signal, std_logic type
b => b(i) -- an out signal, std_logic type
);
end generate;
Now suppose that you want to OR (or whatever) a certain out signal of
the port map of a certain instance with the same signal from all the
instances; in our case a std_logic_vector(PARAMETER downto 0) global_b
which would be:
global_b roberto.ammendola at roma2.infn.it // \
Via della Ricerca Scientifica 1 - 00133 Roma \\_/ //
__________________________________________ ''-.._.-''-.._.. -(||)(')
'''
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Operations within a vector
by Unknown on Apr 20, 2005 |
Not available! | ||
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Roberto,
You can do the following:
variable global_b : std_logic;
...
global_b := '0';
for i in PARAMETER downto 0 loop
for j in VECTOR_SIZE downto 0 loop
global_b := global_b or b(i, j);
end loop;
end loop;
Syntax might not be right but this is the idea...
Regards,
David.
Selon Roberto Ammendola roberto.ammendola at roma2.infn.it>:
A VHDL how-would-you-do-this question (if allowed here).
Suppose you have a parametric generation of instances of a certain
component.
Something like:
inst_generator: for i in 0 to PARAMETER generate
my_inst: component_name
port map(
a => a(i), -- an in signal, std_logic type
b => b(i) -- an out signal, std_logic type
);
end generate;
Now suppose that you want to OR (or whatever) a certain out signal of
the port map of a certain instance with the same signal from all the
instances; in our case a std_logic_vector(PARAMETER downto 0) global_b
which would be:
global_b roberto.ammendola at roma2.infn.it // \
Via della Ricerca Scientifica 1 - 00133 Roma \\_/ //
__________________________________________ ''-.._.-''-.._.. -(||)(')
'''
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
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Operations within a vector
by Unknown on Apr 20, 2005 |
Not available! | ||
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David Brochart wrote:
variable global_b : std_logic;
... global_b := '0'; for i in PARAMETER downto 0 loop for j in VECTOR_SIZE downto 0 loop global_b := global_b or b(i, j); end loop; end loop; thanks David, that's cool. I just wonder if there is a concurrent way to do it. But I am afraid that i am searching for something that (V)HDL can handle only in a sequential statement like above. And anyway I don't think my synthetizer will encounter many troubles to fit it in the timing requirements... well, thanks again Roberto |
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Operations within a vector
by RT on Apr 20, 2005 |
RT
Posts: 10 Joined: Sep 2, 2009 Last seen: Sep 27, 2011 |
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Roberto Ammendola wrote:
A VHDL how-would-you-do-this question (if allowed here).
You'll get better answers from comp.lang.vhdl.
Suppose you have a parametric generation of instances of a certain
component. Something like: signal MYVEC : std_logic_vector(PARAMETER downto 0); begin GLOBAL_B
inst_generator: for i in 0 to PARAMETER generate
my_inst: component_name port map( a => a(i), -- an in signal, std_logic type b => MYVEC(i)
);
end generate; |
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