"Roberto Ammendola" roberto.ammendola at roma2.infn.it> wrote in message news:42665168.3010505 at roma2.infn.it...

You could always use the or_reduce function in std_logic_misc if you have
the appropriate data types, or write your own which would be similar to the
other reply already posted:

---------------

function or_reduce ( vec : std_logic_vector ) return std_logic is
variable result : std_logic := '0';
begin
for i in vec'range loop
result := result or vec(i);
end loop;
end function or_reduce;

---------------

global_b
---------------

That's what I do, because I'm usually not working with std_logic_vector data
types.

- hoffer

"Roberto Ammendola" roberto.ammendola at roma2.infn.it> wrote in message news:426684A9.7060303 at roma2.infn.it...

The above code is "concurrent," as in there is no notion of a clock
anywhere. Wrapping it a function, you can call the function in a concurrent
signal assignment. Putting it process that is sensistive to the appropriate
will make it a concurrent process. Any decent sythesizer should have any
trouble with the for loop. Remember:

a
is no different than:

process is
begin
a wait on b;
end process;

or:

process (b) is
begin
a end process;

or any of the other dozens of ways it could be coded up.

- hoffer