Hi,

I am using the I2C Slave by Steve Fielding. This is connected to a Xilinx AXI IIC IP (v1.02a) which acts as the IIC master transmitter. I have a C code that instructs a uP to R/W the registers of the Xilinx AXI IIC master IP so that transactions are executed.

I always see a NACK after the IIC master IP tries to put the slave device address on to the SDA bus. Even though there is data queued in the tx_fifo of the IIC master. After that NACK ans STOP condition, there is no IIC activity on SDA and SCL.

I have changed the device address in the file i2cSlave_define.v
I am using the 'Dynamic Controller flow logic' of the AXI IIC master IP (Xilinx spec).

For people who have used this slave, can anyone give me an idea why is this so?

Following is the C-code:

int main()
{

//-------------------------------------
// Test AXI_IIC_S0 'Dynamic IIC access'
//-------------------------------------
// 0xc0 menas FIFOs are empty
printf("\n AXI_IIC_SR_S0 = %8x \n", AXI_IIC_SR_S0);

// Initialization
// --------------
RX_FIFO_PIRQ_S0 = 0x0f; // Set rx_fifo depth to max
AXI_IIC_CR_S0 = 0x2; // Reset the TX_FIFO (0000, 010)

// Enable the AXI IIC, remove the TX_FIFO reset, disable the general call (0000, 001)
AXI_IIC_CR_S0 = 0x1;

// Write 4 bytes to an IIC Slave @ 0x34
// -------------------------------------
//AXI_IIC_SR_S0; // Chk all FIFOs empty and bus not busy

// Read the CR
AXI_IIC_CR_S0;

// Set start bit, device address and write access
AXI_IIC_TX_FIFO_S0 = 0x134; // Address of the slave device

AXI_IIC_TX_FIFO_S0 = 0x00; // Register address of the slave for data transfer
AXI_IIC_TX_FIFO_S0 = 0x89; // Byte 1
AXI_IIC_TX_FIFO_S0 = 0xab; // Byte 2
AXI_IIC_TX_FIFO_S0 = 0xcd; // Byte 3
AXI_IIC_TX_FIFO_S0 = 0x2ef; // Byte4 and STOP bit

printf ("\n IIC_s0 operation done, begin IIC_s1 operation!\n");

return 0;
}

Do you have any traces to look at that show what the lines are doing?

Dan

Hi,

Thanks for your response!

Attached is axi_iic.jpg in which you can see the iic transactions being generated by the axi_iic master and is passed to the slave (i2c_s0).
You can see that for the last pluse of scl, sda=1 which means NACK.

You can also see 8 bit data 00110100 or 0x34 being transferred which I have set as the IIC device address, in the i2cSlave_define.v file. I also see the clearStartStopDet signal being asserted just before the NACK and then the iic transactions end.

Also this is what the Philips UM10204 spec says-

There are five conditions that lead to the generation of a NACK:
1. No receiver is present on the bus with the transmitted address so there is no device to
respond with an acknowledge.
2. The receiver is unable to receive or transmit because it is performing some real-time
function and is not ready to start communication with the master.
3. During the transfer, the receiver gets data or commands that it does not understand.
4. During the transfer, the receiver cannot receive any more data bytes.
5. A master-receiver must signal the end of the transfer to the slave transmitter.

, and are ruled out. I do have this IIC slave IP connected and have configured it to br at address 0x34. I also know that the slave is not doing anything in this time when the address is being transmitted. Scenario is inavlid as I have an AXI_IIC IP being the master transmitter.

Thanks for the chart, it really helps out!

Depending on the nomenclature, sometimes addresses are 8 bits with the low order bit reserved for indicating which way the bus is going to go (R/W), and sometimes they are seven bits with the R/W bit tagged on to the end to make 8.

In other words, does this work any better if you send 0x68 for an address instead of a 0x34?

Dan

Take a look at the code in serialInterface.v, and do a search on "I2C_ADDRESS". You'll notice the comparison between input bits [7:1] and the address, and then bit [0] is checked for R/W. That means you need to send, for your address, either 0x68 or 0x69. 0x68 would be the address if you wished to write, and 0x69 if you wished to read.

It looks like this should work. Let me know how it works out for you!

Dan

Hi Dan,

Thanks for your help.

In the define file for the iic slave, the slave address has been set as 7'h34. That means 7 bit addressing is being used.

I tried sending out 0x68, but that didn't help.

You see I was trying to do a write sequence based on the pseudo code given for the axi iic master IP spec by Xilinx (some definite set of bytes need to be written to the master tx. fifo in order to start transmission). They are also using 7 bit addressing for the iic slave.
So I think using 0x134 for slave addressing is ok, when the slave is at address 0x34.

Anyways I think it is very difficult for someone else to debug the code. I have done the top-level and I must solve it.

Regards,
dpaul

Something has gone wrong. No matter what address I send out on the SDA line, I don't see the SM in the iic slave changing states. I need to investigate.
I will reply if I can solve the problem.

Did you ever make any headway on this problem?

Dan

Well no, I gave up on that project due to lack of time. :-(