Hello all! I'm new here but I was wondering if there was a list of projects that need a developer (im new to fpga develpment but I do have an EE degree so my basic tools are all there) but id like to get involved in a project or start my own. I was just wondering the best way to see a list of projects that maybe no one has started or has just kind of died due to lack of interest in development.
Thanks,
Cameron

Have you checked out the projects page? There's a lot of projects on there in various stages of development. If you're looking to step in and do something, look for a project that hasn't been updated in a long time. Is that what you are looking for? Dan

Some other questions for you might be, what's your specific background? What are your interests? Electronics can be a _big_ field. What are you interested in doing? Math co-processing? Video? Low-level hardware interfacing? Music? Lots of possibilities across the board.

Another way to look at things might be, what hardware do you have to work with? If none, what budget do you have? Then, given the hardware, what might you be able to make with it?

There are also projects that you can work on without hardware: simulation types of projects. If you have no hardware, have you checked out Verilator? I've been very pleased with how well I could simulate something without an FPGA synthesis tool.

Just some thoughts,

Dan

Yes thats what im looking for i just didnt know if there was a special place for people to go that allows them to look for developers or help or something.
thanks!

To answer the first question, Im interested in basically anything, I find bitcoin mining on an FPGA interesting but have absolutely no idea how it works, I like the idea of building peripherals like ARM has for their MCU/CPU's.

Also I have a Mojo board by Embedded Micro as my hardware platform and im using Xilinix software suite to write the verilog.

I don't know anything about bitcoin mining either.

I, myself, have been working on "peripherals" as well. Perhaps it's goofy, but having bought a Basys-3 development board, I am now trying to build the "perfect" peripheral driver for each of the peripherals on the board. To date, I have a real-time clock built, a quad-SPI flash controller built, and an internal capabilities expansion port access built. These are posted on OpenCores.

Other capabilities that I have not (yet) posted include an interrupt controller, a wishbone memory (this was trivial), a PS/2 mouse driver, a wishbone accessible "scope" to see what's going on internal to an FPGA, a seven segment display driver, and a serial port driver. Many of these capabilities others have written and posted on Open Cores. I'd like to build an SD-card controller, but I haven't managed to decide what the optimal interface would be to such a controller.

I also had the opportunity to build a display driver that I can use to show power-point type slides on a 640x480 VGA display. The Basys board that I have doesn't really have enough memory to create a video memory, so this was my compromise. This driver decompresses images stored on the flash and displays them on the screen, together with a pointer, and allows mouse or button control of the slides.

Another product I have that I'm really proud of is a serial port to wishbone converter. You'll find others of these here on OpenCores, although the converter I built can drive a 32-bit wishbone bus (32-bits of data, 32-bits of address space), while compressing the transmissions to and from the bus as well. My intent was to use this to debug more difficult interfaces (think Ethernet and PCIe), but I'm still waiting on the funds to purchase a board with one of those more difficult interfaces.

Here's another possibility for you: think of a proprietary core, and see if you can build a non-proprietary version out of "portable" Verilog or VHDL. The non-proprietary version should be able to work with open source simulations, for those who do not have access to the proprietary cores. This was some of my motivation while building an FFT that works at two complex samples per clock. Sadly, I recently bench tested it against Xilinx's FFT core and ... shall we say I was put in my place? I used roughly 9x the resources Xilinx's FFT used. (I expected 2x, since I was essentially doing two FFT's at once, so I've got some work to do ...) Interested in helping?

Here's a suggestion/possibility for you: Can you build a set of "peripheral"s that let you control all aspects of your Mojo board? Some of these might be the ability to set your LED's to any value (on/off) and any dimness, to read the analog pins as "fast" as you can, to control external LED's, and ... after that you might either need some creativity to create peripherals, or purchase some. Alternatively, you might work on something like the "best" fabric multiply, hosting a soft core within an FPGA, or ...

Have I stirred your imagination any?

Maybe I could convince you to try building a better wishbone controlled "scope"?

Dan

Just for discussion, I'm placing what I call a "wishbone scope" into a new project. (You'll need to wait at least a day for the project to get approved and for me to upload it ...) Here's what the scope does:

You place into the scope/core your favorite 32-bits of information from internal to the chip. You can also place into the scope a clock enable line. Thereafter, on every enabled clock, the scope will record a sample of those 32-bits to it's local memory. Next, you set a "trigger", some event that must take place before the data you have placed into the scope is meaningful for you. The last piece of configuration is the holdoff--once the trigger takes place, the scope will continue recording for that many samples/counts before stopping. Once the scope stops, it'll issue an interrupt pulse to any interrupt controller you might have and you can then read all of the bits back out and see what was happening internal to your FPGA.

The entire approach depends upon the existence of a working 32-bit bus and 2 addresses on that bus (one for control, one for data), but after that the core can be exceptionally useful in figuring out what is going on.

I've used this core to debug PS/2 interactions, Q/SPI flash interactions, as well as wishbone bus problems. For the PS/2, I set the core up to trigger on the beginning of a PS/2 command and set the holdoff to almost the full length of the buffer. From here, I discovered that I really misunderstood how PS/2 works. (Oops) For another problem, I was struggling with the wishbone bus locking up. By using a separate bus driver, and controlling which driver controlled the bus through a manual user switch, I could recover the wishbone bus. I then set the scope to trigger off the bus locking up and the holdoff to zero. When the trigger then went off, I could see 2k words of debugging info from before the "event" to see what lead up to it.

Yes, I understand there are proprietary solutions to these problems--many using the JTAG port. This is not that. This is just a simple, pure, Verilog core for debugging and testing.

Now, having given that much intro, here's the problem: while things can change every clock cycle, very often they do not. As an example, the PS/2 device is *much* slower than the FGPA, as is anything commanded by the serial port. This means that many of the values in and out of the scope will be identical. It should be possible to compress the scope's memory therefore so you can see more of what is going on. Say we dropped the number of recorded bits from 32 down to 31 and used the high order bit to determine whether the word that was recorded was either a data word or a number of clock cycles to skip word. The trick is, what happens when the "trigger" takes place internal to a rest period?

Is this starting to sound like an interesting project?

Dan

If you're interested, the project is now listed as a "Wishbone Scope" under the Testing/Verification section of the projects page.

Dan