Hi all,

I'm fpga beginner and working on opalKelly xem6010 with Spartan 6 XEM6010-LX45.

I'm trying to write a verilog code to read and write from ddr2 RAM.

At the moment i created the ram interface with mig generator, but I'm not able to write a simple test bench for write and read data on ram using the mig interface.

Someone could help me indicated some simple examples?

Thank you in advance

As I recall, Xilinx's memory interface generator comes with a spot where you can right click, select from the menu, and then have Xilinx build the test bench for you. Check the documentation for the memory interface generator core. I think you'll find your answer there.

Dan