Hey Guys,

I am not really a CPU designer, but like to be preoccupied with bits and logic gates and I believe I have found the following useful for you. Please bare my unorthodox way of explaining for I am not really from this field. I will explain it in terms of what I understand to be behind some functions in Assembler and please correct me where I am wrong.

When you do INC or DEC, I have been told that full binary adders are used. However, instead of full binary adders you could do the following trick:

For instance. When you are at 101011. And you would currently use the INC command on that, you would be using a full binary adder, but a full binary adder requires to use a serial adder, which needs a cycle for each bit in the register (https://en.wikipedia.org/wiki/Serial_binary_adder). If one would make separate instructions for the INC and DEC commands, then one could make a much simpler circuit to do the following:


Adding:

Step 1 : 001111 -- XOR each bit from the right with 1 UNtil you find the first 0.
Step 2 : 001110
Step 3 : 001100
Step 4 : 001000
Step 5 : 000000
Step 6 : 010000 -- For the initial bit was 0, you stop, for the D-latch (?) will turn to the opposite state of what it was before, when it did continue to flip each bit.

For subtracting one can do the same, but opposite. You XOR each bit from the right with 1 UNtil the first 1.

This is only correct for serial adders (the result bits are computed serially, one bit in every clock cycle). Virtually all adders nowadays are parallel adders (the result bits are computed in a single clock cycle with a separate combinational circuit for each bit). The reason is that time is precious, and gates are very cheap.

Hellwig

So, how does this work? It uses a seperate circuit for INC and DEC or the same circuit as ADD or SUB and using an additional register for adding or substracting with 1? Is there anything where you could point me out to some documentation?

Thanks for your previous reply.

Usually a CPU has an ALU (arithmetic/logic unit) in its data path which is capable of adding two binary two's complement numbers of a given width, e.g. 32 bit. Subtraction is done by adding the bitwise complement of the second operand (and feeding a 1 into the carry input of the least significant bit).

Increment and decrement operations are performed by setting the second operand to 1 (32 bits). This may be done with the help of a separate register, but since the contents of that register are constant, a multiplexer will do.

If you construct an ALU in an HDL (hardware description language), you won't go down to the level of gates however. Typically you have a function input (add, subtract, increment, decrement) besides the two operands. Then you compute the output according to the function input with a case statement (think of it as a multiplexer - but the hardware synthesizer will map that to whatever circuits are available on the chip).

https://en.wikipedia.org/wiki/Arithmetic_logic_unit
John F. Wakerly, Digital Design: Principles and Practices
David A. Patterson, John L. Hennessy, Computer Organization and Design
David Harris, Digital Design and Computer Architecture

Hellwig