Hi everyone,
I am not a designer and I am starting my journey in the Formal Verification world.
I need, for this reason, a verilog implementation of a core, with his RAM memory, ready to start program execution. I have no idea about how to write a complete Verilog architecture that can execute a program. I have to verify software and hardware at the same time but I don't need a specific hardware architecture.
Can anyone help me?

Thanks a lot in advance.

Best Regards,
Francesco

From reading your description above, I'm not sure what you want. Many of the cores available on open cores are subsets of a complete configuration--they will not run by themselves. Some of these cores have and use memory, others do not. Some of these cores execute programs, others just handle pieces of logic.

Can you be more specific about what you are looking for?

Dan

Hi Francesco,

may I point you to our ECO32 system-on-chip project? It consists of a 32-bit processor with a RISC instruction set, kernel/user mode, paging with TLB support, memory controller, and a set of circuits as interfaces to peripherals. We have a simple toolchain (LCC C-compiler, assembler, linker), and recently, we ported the GNU Compiler Collection to ECO32. Right now we are working to get NetBSD running on it, but this is not yet finished.

There is an instruction set simulator as well as a Verilog implementation for FPGAs included in the project, so that programs may be developed independently from hardware. You can find the details here:

http://opencores.org/project,eco32

If you have questions, I will be glad to help.

Hellwig

Hellwig,

That's impressive! I had noticed that the ECO32 project was active recently, and from your description it sounds as though you have been quite busy!

I am also looking at porting the GCC toolchain to a support a project of my own design, and I was wondering if you could share any of your experiences with the process: did you find it very difficult to do?

Thanks,

Dan

Dan,

I worked on and off that project for quite a few years now. It started as a pure simulator, intended as a target for my compiler construction course. Later, FPGAs got big enough to host all the logic, and I started to experiment with real hardware. As soon as I got a parallel ATA ("IDE") interface onto the chip, I could write an operating system to either a hard disk, or more recently, to an SSD. I ported the venerable UNIX 7th Edition to ECO32 (the code is under an open license since 2002, iirc). This OS has the big advantage of being small (the kernel has only around 10000 lines) compared to modern variants, which are at least 10 times bigger.

The main difficulty in writing a back-end for GCC is the state of documentation of the BFD ("binary file descriptor") library. These are routines which handle object files for different architectures (and different object file formats). The BFD part of a port must be written before you can even think of adding a back-end to the compiler. This task has been accomplished by Jens Mehler, an excellent student, now with IBM. Jens will be glad to give you much more detailed information about the whole process.

May I propose to continue off this list in order to avoid hijacking Francesco's thread? We could either open a separate thread or continue privately (hellwig.geisse@mni.thm.de).

Best regards,
Hellwig

Stefan Kristiansson from the OpenRISC project did some stuff for eco32 as well a while ago. He did an alternative CPU core and made some core files so that it can be built and simulated with FuseSoC for the de0 nano. The cores haven't been added to the official FuseSoC core library yet, but you can get it at https://github.com/skristiansson/orpsoc-cores/tree/eco32

Francesco,

Please accept my apologies for taking this thread off topic.

Hellwig,

Thanks for your comments, I'll contact you offline for anything more.

Dan