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Wishbone in UART16550
by Unknown on May 4, 2005
Not available!
Hello, I'm using the UART16550 core and there is something related to the implementation of wishbone that I disagree with. Under uart_top.v are 2 modules: uart_regs.v and uart_wb.v. Wishbone control signals are only provided to uart_wb.v and uart_regs.v receive address and data buses. I'm upsetted with the fact that uart_regs.v doesn't receive the strobe signal. Thus this module drives the output data bus even if the master isn't talking to it (strobe not asserted for this slave). I know that the wb_dat_i input of the master is a muxtiplexing of the wb_dat_o of all slave so it doesn't disturb when a slave drives its wb_dat_o whereas the master is talking to an other slave. However, I think it would be better that wishbone's slaves doesn't have any activity as long as they are not addressed. As I'm a new Wishbone user, I may be wrong. What are Wishbone Wizards thinking about my opinion ? Regards, Fran6 -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20050504/ff99b37d/attachment.htm
Wishbone in UART16550
by Unknown on Jan 4, 2006
Not available!
Hello Francis, I search UART16550 vhdl model of verilog Opencores model. Do you if anybody have this model ? Thanks in advance Henri ----- Original Message ----- From: Ielsch FrancisFrancis.Ielsch at e...> To: Date: Wed May 4 11:01:03 CEST 2005 Subject: [oc] Wishbone in UART16550
Hello,
I'm using the UART16550 core and there is something related to the
implementation of wishbone that I disagree with.
Under uart_top.v are 2 modules: uart_regs.v and uart_wb.v. Wishbone
control signals are only provided to uart_wb.v and uart_regs.v
receive
address and data buses. I'm upsetted with the fact that uart_regs.v
doesn't receive the strobe signal. Thus this module drives the
output
data bus even if the master isn't talking to it (strobe not
asserted for
this slave).
I know that the wb_dat_i input of the master is a muxtiplexing of
the
wb_dat_o of all slave so it doesn't disturb when a slave drives its
wb_dat_o whereas the master is talking to an other slave. However,
I
think it would be better that wishbone's slaves doesn't have any
activity as long as they are not addressed.
As I'm a new Wishbone user, I may be wrong. What are Wishbone
Wizards
thinking about my opinion ?
Regards,
Fran6
-------------- next part --------------
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Wishbone in UART16550
by Unknown on Jan 13, 2006
Not available!
Hi Henri, I think it does only exist in verilog and if your design is already written VHDL then you have to mix VHDL and verilog. Fran6 -----Ursprüngliche Nachricht----- Von: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] Im Auftrag von hbollon at yahoo.fr Gesendet: Mittwoch, 4. Januar 2006 18:40 An: cores at opencores.org Betreff: Re: [oc] Wishbone in UART16550 Hello Francis, I search UART16550 vhdl model of verilog Opencores model. Do you if anybody have this model ? Thanks in advance Henri ----- Original Message ----- From: Ielsch FrancisFrancis.Ielsch at e...> To: Date: Wed May 4 11:01:03 CEST 2005 Subject: [oc] Wishbone in UART16550
Hello,
I'm using the UART16550 core and there is something related to the
implementation of wishbone that I disagree with.
Under uart_top.v are 2 modules: uart_regs.v and uart_wb.v. Wishbone
control signals are only provided to uart_wb.v and uart_regs.v
receive
address and data buses. I'm upsetted with the fact that uart_regs.v
doesn't receive the strobe signal. Thus this module drives the
output
data bus even if the master isn't talking to it (strobe not
asserted for
this slave).
I know that the wb_dat_i input of the master is a muxtiplexing of
the
wb_dat_o of all slave so it doesn't disturb when a slave drives its
wb_dat_o whereas the master is talking to an other slave. However,
I
think it would be better that wishbone's slaves doesn't have any
activity as long as they are not addressed.
As I'm a new Wishbone user, I may be wrong. What are Wishbone
Wizards
thinking about my opinion ?
Regards,
Fran6
-------------- next part --------------
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