OpenCores

OpenCores

OPB2WB wrapper + SPI lite

no use

no use

1/1

no use

no use

OPB2WB wrapper + SPI lite by Unknown on May 4, 2005			Not available!
I am trying to evaluate the OPB2WB wrapper from opencores. I want to connect the wrapper to the OPB bus and to the SPI lite IP. The problem is that the OPB2WB IP has 32 bit address and data interface, but the SPI lite has 2 bit address and 8 bit data interfaces. How can I connect them together. I tryed to modifiy the 2 bit and 8 bit vectors in the verilog source files, and made them to be 32 bit, but it does not work. I have searched a lot for any posts about that, but did not find anything. Any suggestions about how to make the conncections ? Is there anybody that has done a similar working interconnection ? Regards to all !!! Sami -------------- next part -------------- An HTML attachment was scrubbed... URL: <A HREF="http://www.opencores.org/forums.cgi/cores/attachments/20050504/315017f8/attachment.htm">http://www.opencores.org/forums.cgi/cores/attachments/20050504/315017f8/attachment.htm</A> I am trying to evaluate the OPB2WB wrapper from opencores. I want to connect the wrapper to the OPB bus and to the SPI lite IP. The problem is that the OPB2WB IP has 32 bit address and data interface, but the SPI lite has 2 bit address and 8 bit data interfaces. How can I connect them together. I tryed to modifiy the 2 bit and 8 bit vectors in the verilog source files, and made them to be 32 bit, but it does not work. I have searched a lot for any posts about that, but did not find anything. Any suggestions about how to make the conncections ? Is there anybody that has done a similar working interconnection ? Regards to all !!! Sami -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20050504/315017f8/attachment.htm

OPB2WB wrapper + SPI lite by Unknown on May 16, 2005			Not available!
EDK does not allow connection between different size buses, how can I connect the WB 32 bit wrapper to the SPI 8 bit data bus ? ----- Original Message ----- From: secamiei<<A HREF="http://www.opencores.org/mailman/listinfo/cores">secamiei at b...</A>> To: Date: Wed May 4 18:13:07 CEST 2005 Subject: [oc] OPB2WB wrapper + SPI lite [q] I am trying to evaluate the OPB2WB wrapper from opencores. I want to connect the wrapper to the OPB bus and to the SPI lite IP. The problem is that the OPB2WB IP has 32 bit address and data interface, but the SPI lite has 2 bit address and 8 bit data interfaces. How can I connect them together. I tryed to modifiy the 2 bit and 8 bit vectors in the verilog source files, and made them to be 32 bit, but it does not work. I have searched a lot for any posts about that, but did not find anything. Any suggestions about how to make the conncections ? Is there anybody that has done a similar working interconnection ? Regards to all !!! Sami -------------- next part -------------- An HTML attachment was scrubbed... URL: cores/attachments/20050504/315017f8attachment.htm [/q] EDK does not allow connection between different size buses, how can I connect the WB 32 bit wrapper to the SPI 8 bit data bus ? ----- Original Message ----- From: secamieisecamiei at b...> To: Date: Wed May 4 18:13:07 CEST 2005 Subject: [oc] OPB2WB wrapper + SPI lite I am trying to evaluate the OPB2WB wrapper from opencores. I want to connect the wrapper to the OPB bus and to the SPI lite IP. The problem is that the OPB2WB IP has 32 bit address and data interface, but the SPI lite has 2 bit address and 8 bit data interfaces. How can I connect them together. I tryed to modifiy the 2 bit and 8 bit vectors in the verilog source files, and made them to be 32 bit, but it does not work. I have searched a lot for any posts about that, but did not find anything. Any suggestions about how to make the conncections ? Is there anybody that has done a similar working interconnection ? Regards to all !!! Sami -------------- next part -------------- An HTML attachment was scrubbed... URL: cores/attachments/20050504/315017f8attachment.htm

OPB2WB wrapper + SPI lite by Unknown on Jun 1, 2005			Not available!
At 14:51 16/05/2005 +0200, you wrote: [q]EDK does not allow connection between different size buses, how can I connect the WB 32 bit wrapper to the SPI 8 bit data bus ?[/q] Hello Sami, After fixing some problems iÂ´ve used successfully the opb2wb wrapper with a WB core of my own (EDK 7.1). Some of these clues are taken from the FPGA mailing list 0- IÂ´ve changed the data and address vectors of my WB core to adapt it to the 32 buses of the wrapper 1- Download the wrapper from opencores 2 - Copy the wrapper files to pcores directory 3- Change the bbd file to ################################################################################ ## ## Copyright (C) 2000-2004 ASICS World Services, LTD. ## www.asics.ws ## <A HREF="http://www.opencores.org/mailman/listinfo/cores">info at asics.ws</A> ## ## Author: Rudolf Usselmann ## <A HREF="http://www.opencores.org/mailman/listinfo/cores">rudi at asics.ws</A> ## ################################################################################ FILES ################################################################################ opb2wb.edn 3- Rename the .edn to opb2wb.edn 4- Change PORT opb_rst to PORT rst in the .mpd file PORT opb_rst = OPB_Rst, DIR = IN, BUS = SOPB PORT rst = OPB_Rst, DIR = IN, BUS = SOPB 5- Make the rst signal visible in the EDK to check if it is connected to the right reset global signal of your design 6- Edit the edif file to change (program "Xilinx ngc2edif" (version "G.31a")) to (program "none") (As Rudi explains in one of his email, Xilinx documentation about generating exportable netlists is not very clear) 7- Select address 8000 0000 for the wrapper Regards, Armando [q]----- Original Message ----- From: secamiei<<A HREF="http://www.opencores.org/mailman/listinfo/cores">secamiei at b...</A>> To: Date: Wed May 4 18:13:07 CEST 2005 Subject: [oc] OPB2WB wrapper + SPI lite [q]> I am trying to evaluate the OPB2WB wrapper from opencores. I want > to connect the wrapper to the OPB bus and to the SPI lite IP. > The problem is that the OPB2WB IP has 32 bit address and data > interface, but the SPI lite has 2 bit address and 8 bit data > interfaces. > How can I connect them together. I tryed to modifiy the 2 bit and 8 > bit vectors in the verilog source files, and made them to be 32 > bit, but it does not work. > I have searched a lot for any posts about that, but did not find > anything. > Any suggestions about how to make the conncections ? Is there > anybody that has done a similar working interconnection ? > Regards to all !!! > Sami > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: cores/attachments/20050504/315017f8attachment.htm > >[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] ---------------------------------------------------------------------------------------------------------------------- Armando Astarloa CuÃ©llar - Universidad del Pais Vasco UPV/EHU TecnologÃa ElectrÃ³nica Departamento de ElectrÃ³nica y Telecomunicaciones Escuela Superior de Ingenieros - Email: <A HREF="http://www.opencores.org/mailman/listinfo/cores">jtpascua at bi.ehu.es</A> Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04 48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59 URL : <A HREF="http://det.bi.ehu.es/~apert">http://det.bi.ehu.es/~apert</A> ---------------------------------------------------------------------------------------------------------------------- At 14:51 16/05/2005 +0200, you wrote: EDK does not allow connection between different size buses, how can I connect the WB 32 bit wrapper to the SPI 8 bit data bus ? Hello Sami, After fixing some problems iÂ´ve used successfully the opb2wb wrapper with a WB core of my own (EDK 7.1). Some of these clues are taken from the FPGA mailing list 0- IÂ´ve changed the data and address vectors of my WB core to adapt it to the 32 buses of the wrapper 1- Download the wrapper from opencores 2 - Copy the wrapper files to pcores directory 3- Change the bbd file to ################################################################################ ## ## Copyright (C) 2000-2004 ASICS World Services, LTD. ## www.asics.ws ## info at asics.ws ## ## Author: Rudolf Usselmann ## rudi at asics.ws ## ################################################################################ FILES ################################################################################ opb2wb.edn 3- Rename the .edn to opb2wb.edn 4- Change PORT opb_rst to PORT rst in the .mpd file PORT opb_rst = OPB_Rst, DIR = IN, BUS = SOPB PORT rst = OPB_Rst, DIR = IN, BUS = SOPB 5- Make the rst signal visible in the EDK to check if it is connected to the right reset global signal of your design 6- Edit the edif file to change (program "Xilinx ngc2edif" (version "G.31a")) to (program "none") (As Rudi explains in one of his email, Xilinx documentation about generating exportable netlists is not very clear) 7- Select address 8000 0000 for the wrapper Regards, Armando ----- Original Message ----- From: secamieisecamiei at b...> To: Date: Wed May 4 18:13:07 CEST 2005 Subject: [oc] OPB2WB wrapper + SPI lite > I am trying to evaluate the OPB2WB wrapper from opencores. I want > to connect the wrapper to the OPB bus and to the SPI lite IP. > The problem is that the OPB2WB IP has 32 bit address and data > interface, but the SPI lite has 2 bit address and 8 bit data > interfaces. > How can I connect them together. I tryed to modifiy the 2 bit and 8 > bit vectors in the verilog source files, and made them to be 32 > bit, but it does not work. > I have searched a lot for any posts about that, but did not find > anything. > Any suggestions about how to make the conncections ? Is there > anybody that has done a similar working interconnection ? > Regards to all !!! > Sami > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: cores/attachments/20050504/315017f8attachment.htm > > _______________________________________________ http://www.opencores.org/mailman/listinfo/cores ---------------------------------------------------------------------------------------------------------------------- Armando Astarloa CuÃ©llar - Universidad del Pais Vasco UPV/EHU TecnologÃa ElectrÃ³nica Departamento de ElectrÃ³nica y Telecomunicaciones Escuela Superior de Ingenieros - Email: jtpascua at bi.ehu.es Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04 48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59 URL : http://det.bi.ehu.es/~apert ----------------------------------------------------------------------------------------------------------------------

OPB2WB wrapper + SPI lite by Unknown on Jun 1, 2005			Not available!
Hi Armando, I used the same solution as you, and the OPB2WB wrapper works. But now there is one other problem. The wrapper works only if I try to write to the 0x80000000 address. If I change the address range of the OPB2WB wrapper in EDK to in example 0x80018000, the OPB2WB does not work, I mean it does not assert CYC and STB signals. I tryed to change the PARAMETER C_BASEADDR=32'h8000_0000 C_HIGHADDR=0x800000ff to C_BASEADDR=0x80018000 C_HIGHADDR=0x800180ff, but it does not work. It works always only if I write to 0x80000000. This is a problem because if I use 2 WB cores, it means that I need 2 wrappers in EDK, but they must have different address ranges, otherwise all data will be sent to both cores. But the wrappers works only in the same address range 0x80000000 -> 0x800000ff . I hope I was clear in my explanation. Thanks for any suggestion. Regards Sami (secamiei) ----- Original Message ----- From: Armando Astarloa<<A HREF="http://www.opencores.org/mailman/listinfo/cores">jtpascua at b...</A>> To: Date: Wed Jun 1 12:22:33 CEST 2005 Subject: [oc] OPB2WB wrapper + SPI lite [q] At 14:51 16/05/2005 +0200, you wrote: [q]>EDK does not allow connection between different size buses, how [/q] can I [q]>connect the WB 32 bit wrapper to the SPI 8 bit data bus ? [/q] Hello Sami, After fixing some problems iÂ´ve used successfully the opb2wb wrapper with a WB core of my own (EDK 7.1). Some of these clues are taken from the FPGA mailing list 0- IÂ´ve changed the data and address vectors of my WB core to adapt it to the 32 buses of the wrapper 1- Download the wrapper from opencores 2 - Copy the wrapper files to pcores directory 3- Change the bbd file to [/q] ################################################################################ [q] ## ## Copyright (C) 2000-2004 ASICS World Services, LTD. ## www.asics.ws ## <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] ---------------------------------------------------------------------------------------------------------------------- [q] Armando Astarloa CuÃ©llar - Universidad del Pais Vasco UPV/EHU TecnologÃa ElectrÃ³nica Departamento de ElectrÃ³nica y Telecomunicaciones Escuela Superior de Ingenieros - Email: jtpascua at bi.ehu.es Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04 48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59 URL : ~apert [/q] ---------------------------------------------------------------------------------------------------------------------- [q] [/q] Hi Armando, I used the same solution as you, and the OPB2WB wrapper works. But now there is one other problem. The wrapper works only if I try to write to the 0x80000000 address. If I change the address range of the OPB2WB wrapper in EDK to in example 0x80018000, the OPB2WB does not work, I mean it does not assert CYC and STB signals. I tryed to change the PARAMETER C_BASEADDR=32'h8000_0000 C_HIGHADDR=0x800000ff to C_BASEADDR=0x80018000 C_HIGHADDR=0x800180ff, but it does not work. It works always only if I write to 0x80000000. This is a problem because if I use 2 WB cores, it means that I need 2 wrappers in EDK, but they must have different address ranges, otherwise all data will be sent to both cores. But the wrappers works only in the same address range 0x80000000 -> 0x800000ff . I hope I was clear in my explanation. Thanks for any suggestion. Regards Sami (secamiei) ----- Original Message ----- From: Armando Astarloajtpascua at b...> To: Date: Wed Jun 1 12:22:33 CEST 2005 Subject: [oc] OPB2WB wrapper + SPI lite At 14:51 16/05/2005 +0200, you wrote: >EDK does not allow connection between different size buses, how can I >connect the WB 32 bit wrapper to the SPI 8 bit data bus ? Hello Sami, After fixing some problems iÂ´ve used successfully the opb2wb wrapper with a WB core of my own (EDK 7.1). Some of these clues are taken from the FPGA mailing list 0- IÂ´ve changed the data and address vectors of my WB core to adapt it to the 32 buses of the wrapper 1- Download the wrapper from opencores 2 - Copy the wrapper files to pcores directory 3- Change the bbd file to ################################################################################ ## ## Copyright (C) 2000-2004 ASICS World Services, LTD. ## www.asics.ws ## http://www.opencores.org/mailman/listinfo/cores ---------------------------------------------------------------------------------------------------------------------- Armando Astarloa CuÃ©llar - Universidad del Pais Vasco UPV/EHU TecnologÃa ElectrÃ³nica Departamento de ElectrÃ³nica y Telecomunicaciones Escuela Superior de Ingenieros - Email: jtpascua at bi.ehu.es Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04 48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59 URL : ~apert ----------------------------------------------------------------------------------------------------------------------

OPB2WB wrapper + SPI lite by Unknown on Jun 1, 2005			Not available!
Hello Sami, I dont know if it is possible to change that address, because what we have is the netlist, not the source code. Who could answer that question is Rudolff who made it. If different address is used, you can check with the OPB-Chipscope that the opb transfer is not acknoledge and the timeout signal is set. One solution is not to wrapp a single core but a Wishbone system (including a memory decoder with one stb and address at the input, and the strobes for the different cores at the output). Regards, Armando At 16:46 01/06/2005 +0200, you wrote: [q]Hi Armando, I used the same solution as you, and the OPB2WB wrapper works. But now there is one other problem. The wrapper works only if I try to write to the 0x80000000 address. If I change the address range of the OPB2WB wrapper in EDK to in example 0x80018000, the OPB2WB does not work, I mean it does not assert CYC and STB signals. I tryed to change the PARAMETER C_BASEADDR=32'h8000_0000 C_HIGHADDR=0x800000ff to C_BASEADDR=0x80018000 C_HIGHADDR=0x800180ff, but it does not work. It works always only if I write to 0x80000000. This is a problem because if I use 2 WB cores, it means that I need 2 wrappers in EDK, but they must have different address ranges, otherwise all data will be sent to both cores. But the wrappers works only in the same address range 0x80000000 -> 0x800000ff . I hope I was clear in my explanation. Thanks for any suggestion. Regards Sami (secamiei) ----- Original Message ----- From: Armando Astarloa<<A HREF="http://www.opencores.org/mailman/listinfo/cores">jtpascua at b...</A>> To: Date: Wed Jun 1 12:22:33 CEST 2005 Subject: [oc] OPB2WB wrapper + SPI lite [q]> At 14:51 16/05/2005 +0200, you wrote: [q] >EDK does not allow connection between different size buses, how[/q] > can I [q] >connect the WB 32 bit wrapper to the SPI 8 bit data bus ?[/q] > Hello Sami, > After fixing some problems iÂ´ve used successfully the opb2wb > wrapper with a WB core of my own (EDK 7.1). > Some of these clues are taken from the FPGA mailing list > 0- IÂ´ve changed the data and address vectors of my WB core to > adapt it to > the 32 buses of the wrapper > 1- Download the wrapper from opencores > 2 - Copy the wrapper files to pcores directory > 3- Change the bbd file to > >[/q] ################################################################################ [q]> ## > ## Copyright (C) 2000-2004 ASICS World Services, LTD. > ## www.asics.ws > ## <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> > >[/q] ---------------------------------------------------------------------------------------------------------------------- [q]> Armando Astarloa CuÃ©llar - Universidad del Pais Vasco UPV/EHU > TecnologÃa ElectrÃ³nica > Departamento de ElectrÃ³nica y Telecomunicaciones > Escuela Superior de Ingenieros - Email: jtpascua at bi.ehu.es > Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04 > 48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59 > URL : ~apert > >[/q] ---------------------------------------------------------------------------------------------------------------------- [q]> >[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] ---------------------------------------------------------------------------------------------------------------------- Armando Astarloa CuÃ©llar - Universidad del Pais Vasco UPV/EHU TecnologÃa ElectrÃ³nica Departamento de ElectrÃ³nica y Telecomunicaciones Escuela Superior de Ingenieros - Email: <A HREF="http://www.opencores.org/mailman/listinfo/cores">jtpascua at bi.ehu.es</A> Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04 48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59 URL : <A HREF="http://det.bi.ehu.es/~apert">http://det.bi.ehu.es/~apert</A> ---------------------------------------------------------------------------------------------------------------------- Hello Sami, I dont know if it is possible to change that address, because what we have is the netlist, not the source code. Who could answer that question is Rudolff who made it. If different address is used, you can check with the OPB-Chipscope that the opb transfer is not acknoledge and the timeout signal is set. One solution is not to wrapp a single core but a Wishbone system (including a memory decoder with one stb and address at the input, and the strobes for the different cores at the output). Regards, Armando At 16:46 01/06/2005 +0200, you wrote: Hi Armando, I used the same solution as you, and the OPB2WB wrapper works. But now there is one other problem. The wrapper works only if I try to write to the 0x80000000 address. If I change the address range of the OPB2WB wrapper in EDK to in example 0x80018000, the OPB2WB does not work, I mean it does not assert CYC and STB signals. I tryed to change the PARAMETER C_BASEADDR=32'h8000_0000 C_HIGHADDR=0x800000ff to C_BASEADDR=0x80018000 C_HIGHADDR=0x800180ff, but it does not work. It works always only if I write to 0x80000000. This is a problem because if I use 2 WB cores, it means that I need 2 wrappers in EDK, but they must have different address ranges, otherwise all data will be sent to both cores. But the wrappers works only in the same address range 0x80000000 -> 0x800000ff . I hope I was clear in my explanation. Thanks for any suggestion. Regards Sami (secamiei) ----- Original Message ----- From: Armando Astarloajtpascua at b...> To: Date: Wed Jun 1 12:22:33 CEST 2005 Subject: [oc] OPB2WB wrapper + SPI lite > At 14:51 16/05/2005 +0200, you wrote: >EDK does not allow connection between different size buses, how > can I >connect the WB 32 bit wrapper to the SPI 8 bit data bus ? > Hello Sami, > After fixing some problems iÂ´ve used successfully the opb2wb > wrapper with a WB core of my own (EDK 7.1). > Some of these clues are taken from the FPGA mailing list > 0- IÂ´ve changed the data and address vectors of my WB core to > adapt it to > the 32 buses of the wrapper > 1- Download the wrapper from opencores > 2 - Copy the wrapper files to pcores directory > 3- Change the bbd file to > > ################################################################################ > ## > ## Copyright (C) 2000-2004 ASICS World Services, LTD. > ## www.asics.ws > ## http://www.opencores.org/mailman/listinfo/cores > > ---------------------------------------------------------------------------------------------------------------------- > Armando Astarloa CuÃ©llar - Universidad del Pais Vasco UPV/EHU > TecnologÃa ElectrÃ³nica > Departamento de ElectrÃ³nica y Telecomunicaciones > Escuela Superior de Ingenieros - Email: jtpascua at bi.ehu.es > Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04 > 48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59 > URL : ~apert > > ---------------------------------------------------------------------------------------------------------------------- > > _______________________________________________ http://www.opencores.org/mailman/listinfo/cores ---------------------------------------------------------------------------------------------------------------------- Armando Astarloa CuÃ©llar - Universidad del Pais Vasco UPV/EHU TecnologÃa ElectrÃ³nica Departamento de ElectrÃ³nica y Telecomunicaciones Escuela Superior de Ingenieros - Email: jtpascua at bi.ehu.es Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04 48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59 URL : http://det.bi.ehu.es/~apert ----------------------------------------------------------------------------------------------------------------------

OPB2WB wrapper + SPI lite by Unknown on Jun 2, 2005			Not available!
I checked with Chipscope, and the transfer is acknowledged only when the address is in range 0x80000000 ->0x800000ff. If you change the address in EDK, and you write to that address, the transfer is not acknowledged. Now I am trying to build a system with 2 SPI cores (attached to the OPB with 2 OPB2WB wrappers). I assigned in EDK 0x80000000->0x800000ff to the first OPB2WB wrapper (connected to the first SPI core) and 0x80000100->0x800001ff. I hope the wrappers will accept those address ranges. ----- Original Message ----- From: Armando Astarloa<<A HREF="http://www.opencores.org/mailman/listinfo/cores">jtpascua at b...</A>> To: Date: Wed Jun 1 17:38:18 CEST 2005 Subject: [oc] OPB2WB wrapper + SPI lite [q] Hello Sami, I dont know if it is possible to change that address, because what we have is the netlist, not the source code. Who could answer that question is Rudolff who made it. If different address is used, you can check with the OPB-Chipscope that the opb transfer is not acknoledge and the timeout signal is set. One solution is not to wrapp a single core but a Wishbone system (including a memory decoder with one stb and address at the input, and the strobes for the different cores at the output). Regards, Armando At 16:46 01/06/2005 +0200, you wrote: [q]>Hi Armando, > >I used the same solution as you, and the OPB2WB wrapper works. >But now there is one other problem. The wrapper works only if I [/q] try to [q]>write to the 0x80000000 address. If I change the address range [/q] of the [q]>OPB2WB wrapper in EDK to in example 0x80018000, the OPB2WB does [/q] not [q]>work, I mean it does not assert CYC and STB signals. I tryed to [/q] change [q]>the PARAMETER C_BASEADDR=32'h8000_0000 C_HIGHADDR=0x800000ff to >C_BASEADDR=0x80018000 C_HIGHADDR=0x800180ff, but it does not [/q] work. [q]>It works always only if I write to 0x80000000. >This is a problem because if I use 2 WB cores, it means that I [/q] need 2 [q]>wrappers in EDK, but they must have different address ranges, >otherwise all data will be sent to both cores. But the wrappers [/q] works [q]>only in the same address range 0x80000000 -> 0x800000ff . >I hope I was clear in my explanation. >Thanks for any suggestion. >Regards > >Sami (secamiei) >----- Original Message ----- >From: Armando Astarloa<jtpascua at b...> >To: >Date: Wed Jun 1 12:22:33 CEST 2005 >Subject: [oc] OPB2WB wrapper + SPI lite > [q] > At 14:51 16/05/2005 +0200, you wrote: [q]> >EDK does not allow connection between different size [/q] buses, how [q] > can I [q]> >connect the WB 32 bit wrapper to the SPI 8 bit data [/q] bus ? [q] > Hello Sami, > After fixing some problems iÂ´ve used successfully [/q] the opb2wb [q] > wrapper with a WB core of my own (EDK 7.1). > Some of these clues are taken from the FPGA mailing list > 0- IÂ´ve changed the data and address vectors of my [/q] WB core to [q] > adapt it to > the 32 buses of the wrapper > 1- Download the wrapper from opencores > 2 - Copy the wrapper files to pcores directory > 3- Change the bbd file to > > [/q] ################################################################################[/q] [q]> [q] > ## > ## Copyright (C) 2000-2004 ASICS World Services, LTD. > ## www.asics.ws > ## <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> > > [/q] ----------------------------------------------------------------------------------------------------------------------[/q] [q]> [q] > Armando Astarloa CuÃ©llar - Universidad del Pais [/q] Vasco UPV/EHU [q] > TecnologÃa ElectrÃ³nica > Departamento de ElectrÃ³nica y Telecomunicaciones > Escuela Superior de Ingenieros - Email: jtpascua at [/q] bi.ehu.es [q] > Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04 > 48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59 > URL : ~apert > > [/q] ----------------------------------------------------------------------------------------------------------------------[/q] [q]> [q] > > [/q] >_______________________________________________ ><A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] [/q] ---------------------------------------------------------------------------------------------------------------------- [q] Armando Astarloa CuÃ©llar - Universidad del Pais Vasco UPV/EHU TecnologÃa ElectrÃ³nica Departamento de ElectrÃ³nica y Telecomunicaciones Escuela Superior de Ingenieros - Email: jtpascua at bi.ehu.es Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04 48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59 URL : <A HREF="http://det.bi.ehu.es/~apert">http://det.bi.ehu.es/~apert</A> [/q] ---------------------------------------------------------------------------------------------------------------------- [q] [/q] I checked with Chipscope, and the transfer is acknowledged only when the address is in range 0x80000000 ->0x800000ff. If you change the address in EDK, and you write to that address, the transfer is not acknowledged. Now I am trying to build a system with 2 SPI cores (attached to the OPB with 2 OPB2WB wrappers). I assigned in EDK 0x80000000->0x800000ff to the first OPB2WB wrapper (connected to the first SPI core) and 0x80000100->0x800001ff. I hope the wrappers will accept those address ranges. ----- Original Message ----- From: Armando Astarloajtpascua at b...> To: Date: Wed Jun 1 17:38:18 CEST 2005 Subject: [oc] OPB2WB wrapper + SPI lite Hello Sami, I dont know if it is possible to change that address, because what we have is the netlist, not the source code. Who could answer that question is Rudolff who made it. If different address is used, you can check with the OPB-Chipscope that the opb transfer is not acknoledge and the timeout signal is set. One solution is not to wrapp a single core but a Wishbone system (including a memory decoder with one stb and address at the input, and the strobes for the different cores at the output). Regards, Armando At 16:46 01/06/2005 +0200, you wrote: >Hi Armando, > >I used the same solution as you, and the OPB2WB wrapper works. >But now there is one other problem. The wrapper works only if I try to >write to the 0x80000000 address. If I change the address range of the >OPB2WB wrapper in EDK to in example 0x80018000, the OPB2WB does not >work, I mean it does not assert CYC and STB signals. I tryed to change >the PARAMETER C_BASEADDR=32'h8000_0000 C_HIGHADDR=0x800000ff to >C_BASEADDR=0x80018000 C_HIGHADDR=0x800180ff, but it does not work. >It works always only if I write to 0x80000000. >This is a problem because if I use 2 WB cores, it means that I need 2 >wrappers in EDK, but they must have different address ranges, >otherwise all data will be sent to both cores. But the wrappers works >only in the same address range 0x80000000 -> 0x800000ff . >I hope I was clear in my explanation. >Thanks for any suggestion. >Regards > >Sami (secamiei) >----- Original Message ----- >From: Armando Astarloa >To: >Date: Wed Jun 1 12:22:33 CEST 2005 >Subject: [oc] OPB2WB wrapper + SPI lite > > At 14:51 16/05/2005 +0200, you wrote: > >EDK does not allow connection between different size buses, how > can I > >connect the WB 32 bit wrapper to the SPI 8 bit data bus ? > Hello Sami, > After fixing some problems iÂ´ve used successfully the opb2wb > wrapper with a WB core of my own (EDK 7.1). > Some of these clues are taken from the FPGA mailing list > 0- IÂ´ve changed the data and address vectors of my WB core to > adapt it to > the 32 buses of the wrapper > 1- Download the wrapper from opencores > 2 - Copy the wrapper files to pcores directory > 3- Change the bbd file to > > ################################################################################ > > ## > ## Copyright (C) 2000-2004 ASICS World Services, LTD. > ## www.asics.ws > ## http://www.opencores.org/mailman/listinfo/cores > > ---------------------------------------------------------------------------------------------------------------------- > > Armando Astarloa CuÃ©llar - Universidad del Pais Vasco UPV/EHU > TecnologÃa ElectrÃ³nica > Departamento de ElectrÃ³nica y Telecomunicaciones > Escuela Superior de Ingenieros - Email: jtpascua at bi.ehu.es > Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04 > 48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59 > URL : ~apert > > ---------------------------------------------------------------------------------------------------------------------- > > > >_______________________________________________ >http://www.opencores.org/mailman/listinfo/cores ---------------------------------------------------------------------------------------------------------------------- Armando Astarloa CuÃ©llar - Universidad del Pais Vasco UPV/EHU TecnologÃa ElectrÃ³nica Departamento de ElectrÃ³nica y Telecomunicaciones Escuela Superior de Ingenieros - Email: jtpascua at bi.ehu.es Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04 48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59 URL : http://det.bi.ehu.es/~apert ----------------------------------------------------------------------------------------------------------------------

OPB2WB wrapper + SPI lite by Unknown on Jun 2, 2005			Not available!
On Thu, 2005-06-02 at 15:42 +0200, <A HREF="http://www.opencores.org/mailman/listinfo/cores">secamiei at bigfoot.com</A> wrote: [q] I checked with Chipscope, and the transfer is acknowledged only when the address is in range 0x80000000 ->0x800000ff. If you change the address in EDK, and you write to that address, the transfer is not acknowledged. Now I am trying to build a system with 2 SPI cores (attached to the OPB with 2 OPB2WB wrappers). I assigned in EDK 0x80000000->0x800000ff to the first OPB2WB wrapper (connected to the first SPI core) and 0x80000100->0x800001ff. I hope the wrappers will accept those address ranges.[/q] The problem is that when I ship a netlist version of this wrapper, the parameters C_BASEADDR and C_HIGHADDR get compiled in to the netlist. I honestly do not know how to work around this problem. One way would be provide a non OPB input "SELECT" which would force the address decoding outside the core, but would require another level of abstraction. If somebody could figure out how to solve this problem, I would be happy to create a new release of the OPB/WB wrapper ... Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, <A HREF="http://www.asics.ws">http://www.asics.ws</A> Your Partner for IP Cores, Design, Verification and Synthesis On Thu, 2005-06-02 at 15:42 +0200, secamiei at bigfoot.com wrote: I checked with Chipscope, and the transfer is acknowledged only when the address is in range 0x80000000 ->0x800000ff. If you change the address in EDK, and you write to that address, the transfer is not acknowledged. Now I am trying to build a system with 2 SPI cores (attached to the OPB with 2 OPB2WB wrappers). I assigned in EDK 0x80000000->0x800000ff to the first OPB2WB wrapper (connected to the first SPI core) and 0x80000100->0x800001ff. I hope the wrappers will accept those address ranges. The problem is that when I ship a netlist version of this wrapper, the parameters C_BASEADDR and C_HIGHADDR get compiled in to the netlist. I honestly do not know how to work around this problem. One way would be provide a non OPB input "SELECT" which would force the address decoding outside the core, but would require another level of abstraction. If somebody could figure out how to solve this problem, I would be happy to create a new release of the OPB/WB wrapper ... Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis

OPB2WB wrapper + SPI lite by Unknown on Jun 6, 2005			Not available!
Hi Rudy, is it possible to have the Verilog Source code of that project, because I would like to add an address decoding module, and I need to see how the OPB2WB wrapper works internally. Now I am working on simple address decoder, that takes the address specified in EDK and it simply takes the upper side of that address and substitutes it with a 0x800000xx. I hope it will work. Regards Sami (secamiei) ----- Original Message ----- From: Rudolf Usselmann<<A HREF="http://www.opencores.org/mailman/listinfo/cores">rudi at a...</A>> To: Date: Thu Jun 2 20:11:21 CEST 2005 Subject: [oc] OPB2WB wrapper + SPI lite [q] On Thu, 2005-06-02 at 15:42 +0200, secamiei at bigfoot.com wrote: [q]> I checked with Chipscope, and the transfer is acknowledged [/q] only when [q]> the address is in range 0x80000000 ->0x800000ff. If you [/q] change the [q]> address in > EDK, and you write to that address, the transfer is not [/q] acknowledged. [q]> Now I am trying to build a system with 2 SPI cores (attached [/q] to the [q]> OPB with 2 OPB2WB wrappers). I assigned in EDK [/q] 0x80000000->0x800000ff [q]> to the first OPB2WB wrapper (connected to the first SPI core) [/q] and [q]> 0x80000100->0x800001ff. I hope the wrappers will accept [/q] those address [q]> ranges. [/q] The problem is that when I ship a netlist version of this wrapper, the parameters C_BASEADDR and C_HIGHADDR get compiled in to the netlist. I honestly do not know how to work around this problem. One way would be provide a non OPB input "SELECT" which would force the address decoding outside the core, but would require another level of abstraction. If somebody could figure out how to solve this problem, I would be happy to create a new release of the OPB/WB wrapper ... Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, <A HREF="http://www.asics.ws">http://www.asics.ws</A> Your Partner for IP Cores, Design, Verification and Synthesis [/q] Hi Rudy, is it possible to have the Verilog Source code of that project, because I would like to add an address decoding module, and I need to see how the OPB2WB wrapper works internally. Now I am working on simple address decoder, that takes the address specified in EDK and it simply takes the upper side of that address and substitutes it with a 0x800000xx. I hope it will work. Regards Sami (secamiei) ----- Original Message ----- From: Rudolf Usselmannrudi at a...> To: Date: Thu Jun 2 20:11:21 CEST 2005 Subject: [oc] OPB2WB wrapper + SPI lite On Thu, 2005-06-02 at 15:42 +0200, secamiei at bigfoot.com wrote: > I checked with Chipscope, and the transfer is acknowledged only when > the address is in range 0x80000000 ->0x800000ff. If you change the > address in > EDK, and you write to that address, the transfer is not acknowledged. > Now I am trying to build a system with 2 SPI cores (attached to the > OPB with 2 OPB2WB wrappers). I assigned in EDK 0x80000000->0x800000ff > to the first OPB2WB wrapper (connected to the first SPI core) and > 0x80000100->0x800001ff. I hope the wrappers will accept those address > ranges. The problem is that when I ship a netlist version of this wrapper, the parameters C_BASEADDR and C_HIGHADDR get compiled in to the netlist. I honestly do not know how to work around this problem. One way would be provide a non OPB input "SELECT" which would force the address decoding outside the core, but would require another level of abstraction. If somebody could figure out how to solve this problem, I would be happy to create a new release of the OPB/WB wrapper ... Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis

OPB2WB wrapper + SPI lite by Unknown on Sep 21, 2005			Not available!
Hello, I am wrapping the Ethernet 10/1000 opencores IP with OPB2WB fot the slave WB if and WB2OPB for the master WB. Although the resulting design is synthesizable, the memory range for the OPB2WB (00h-FFh) is not big enough for that core (it needs from 0x000h to 0x7ff). Is possible the extension? Thanks, Armando At 01:11 03/06/2005 +0700, you wrote: [q]On Thu, 2005-06-02 at 15:42 +0200, <A HREF="http://www.opencores.org/mailman/listinfo/cores">secamiei at bigfoot.com</A> wrote: [q]> I checked with Chipscope, and the transfer is acknowledged only when > the address is in range 0x80000000 ->0x800000ff. If you change the > address in > EDK, and you write to that address, the transfer is not acknowledged. > Now I am trying to build a system with 2 SPI cores (attached to the > OPB with 2 OPB2WB wrappers). I assigned in EDK 0x80000000->0x800000ff > to the first OPB2WB wrapper (connected to the first SPI core) and > 0x80000100->0x800001ff. I hope the wrappers will accept those address > ranges.[/q] The problem is that when I ship a netlist version of this wrapper, the parameters C_BASEADDR and C_HIGHADDR get compiled in to the netlist. I honestly do not know how to work around this problem. One way would be provide a non OPB input "SELECT" which would force the address decoding outside the core, but would require another level of abstraction. If somebody could figure out how to solve this problem, I would be happy to create a new release of the OPB/WB wrapper ... Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, <A HREF="http://www.asics.ws">http://www.asics.ws</A> Your Partner for IP Cores, Design, Verification and Synthesis _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] ---------------------------------------------------------------------------------------------------------------------- Armando Astarloa CuÃ©llar - Universidad del Pais Vasco UPV/EHU TecnologÃa ElectrÃ³nica Departamento de ElectrÃ³nica y Telecomunicaciones Escuela Superior de Ingenieros - Email: <A HREF="http://www.opencores.org/mailman/listinfo/cores">jtpascua at bi.ehu.es</A> Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04 48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59 URL : <A HREF="http://det.bi.ehu.es/~apert">http://det.bi.ehu.es/~apert</A> ---------------------------------------------------------------------------------------------------------------------- Hello, I am wrapping the Ethernet 10/1000 opencores IP with OPB2WB fot the slave WB if and WB2OPB for the master WB. Although the resulting design is synthesizable, the memory range for the OPB2WB (00h-FFh) is not big enough for that core (it needs from 0x000h to 0x7ff). Is possible the extension? Thanks, Armando At 01:11 03/06/2005 +0700, you wrote: On Thu, 2005-06-02 at 15:42 +0200, secamiei at bigfoot.com wrote: > I checked with Chipscope, and the transfer is acknowledged only when > the address is in range 0x80000000 ->0x800000ff. If you change the > address in > EDK, and you write to that address, the transfer is not acknowledged. > Now I am trying to build a system with 2 SPI cores (attached to the > OPB with 2 OPB2WB wrappers). I assigned in EDK 0x80000000->0x800000ff > to the first OPB2WB wrapper (connected to the first SPI core) and > 0x80000100->0x800001ff. I hope the wrappers will accept those address > ranges. The problem is that when I ship a netlist version of this wrapper, the parameters C_BASEADDR and C_HIGHADDR get compiled in to the netlist. I honestly do not know how to work around this problem. One way would be provide a non OPB input "SELECT" which would force the address decoding outside the core, but would require another level of abstraction. If somebody could figure out how to solve this problem, I would be happy to create a new release of the OPB/WB wrapper ... Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis _______________________________________________ http://www.opencores.org/mailman/listinfo/cores ---------------------------------------------------------------------------------------------------------------------- Armando Astarloa CuÃ©llar - Universidad del Pais Vasco UPV/EHU TecnologÃa ElectrÃ³nica Departamento de ElectrÃ³nica y Telecomunicaciones Escuela Superior de Ingenieros - Email: jtpascua at bi.ehu.es Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04 48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59 URL : http://det.bi.ehu.es/~apert ----------------------------------------------------------------------------------------------------------------------

no use

no use

1/1

no use

no use

© copyright 1999-2026 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.