FFG is a tool that generates Verilog code for FIR filters. It is based on the RADIX-2r multiple constant multiplication (MCM) algorithm. The Verilog code leads to high-performance results in speed, power, and area, whether mapped on ASIC or FPGA. Benchmarking results using a 65nm CMOS technology confirmed the superiority of RADIX-2r MCM over the existing algorithms.
You can experiment the Automatic Generator of Verilog Code for FIR Filters on the following link:
http://www.cdta.dz/products/mcm/