i need to know how to connect spi master and slave between 2fpga for nexys3

It's not all that hard: the master controls/drives three wires, the slave drives one. You can Google the timing/wiring diagrams and get a boatload of info. Beyond that, read up on the device you are trying to interface with. There are some variations in the standard you'll need to be aware of for your particular device.

Yours,

Dan

thank u man so much . http://opencores.org/project,spi_master_slave
can this project run between 2 nexys3 boards and what about the ucf file ?

im trying to run spi master first on nexys3 but i got confiused with ucf can u help me?

what about the ucf just i need to locate in it the 3 wire that goes to slave fpga , im but in this thing can u help me?

As I understand the SPI project you mention above, it should be able to handle SPI communication between your two boards. However, I have personally never used it--so I'm not sure I can be of much more help there.

The UCF file is something you get from the board manufacturer. You can comment out lines defining pins you don't expect to use, and rename wires that you wish to give to a particular purpose. These are the easy changes, and most of the changes I've ever needed to make.

You'll need to identify pins from each of your boards that you wish to use for this purpose. I would then suggest renaming them in your UCF file so that you remember what pins these are.

Will you be repurposing a PMOD connector for your transfer?

Yours,

Dan

yes sir im gonna use PMOD connector for my transfer but my problem is when im tried to implement the spi master on fpga or slave on fpga i didnt got any relation between the leds and switch or anything this is my my ucf file for master fpga


## Leds
#Net "m_spi_ssel_o" LOC = U16 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L2P_CMPCLK, Sch name = LD0
#Net "m_spi_sck_o" LOC = V16 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L2N_CMPMOSI, Sch name = LD1
#Net "m_spi_mosi_o" LOC = U15 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L5P, Sch name = LD2
#Net "m_di_reg_o" LOC = V15 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L5N, Sch name = LD3
#Net "m_wr_ack_o" LOC = M11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L15P, Sch name = LD4
#Net "m_do_valid_o" LOC = N11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L15N, Sch name = LD5
#Net "m_do_o" LOC = R11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L16P, Sch name = LD6
#Net "Led" LOC = T11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L16N_VREF, Sch name = LD7

## Switches
#Net "m_sclk_i" LOC = T10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L29N_GCLK2, Sch name = SW0
#Net "m_pclk_i" LOC = T9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32P_GCLK29, Sch name = SW1
#Net "m_rst_i" LOC = V9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32N_GCLK28, Sch name = SW2
#Net "m_spi_miso_i" LOC = M8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40P, Sch name = SW3
#Net "m_di_i" LOC = N8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40N, Sch name = SW4
#Net "m_wren_i" LOC = U8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41P, Sch name = SW5
#Net "sw" LOC = V8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41N_VREF, Sch name = SW6
#Net "sw" LOC = T5 | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW7


or sir can can u msg me on my eamil : ananhasasneh1@gmail.com
thanks alot for everything

and there is the ports

entity spi_loopback is
Generic (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '1'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2; -- prefetch lookahead cycles
SPI_2X_CLK_DIV : positive := 5 -- for a 100MHz sclk_i, yields a 10MHz SCK
);
Port(
----------------MASTER-----------------------
m_clk_i : IN std_logic;
m_rst_i : IN std_logic;
m_spi_ssel_o : OUT std_logic;
m_spi_sck_o : OUT std_logic;
m_spi_mosi_o : OUT std_logic;
m_spi_miso_i : IN std_logic;
m_di_req_o : OUT std_logic;
m_di_i : IN std_logic_vector(N-1 downto 0);
m_wren_i : IN std_logic;
m_do_valid_o : OUT std_logic;
m_do_o : OUT std_logic_vector(N-1 downto 0);
----- debug -----
m_do_transfer_o : OUT std_logic;
m_wren_o : OUT std_logic;
m_wren_ack_o : OUT std_logic;
m_rx_bit_reg_o : OUT std_logic;
m_state_dbg_o : OUT std_logic_vector(3 downto 0);
m_core_clk_o : OUT std_logic;
m_core_n_clk_o : OUT std_logic;
m_sh_reg_dbg_o : OUT std_logic_vector(N-1 downto 0)

);
end spi_loopback;

There is also a wonderful SPI tutorial at fpga4fun.com. If you haven't seen it, you might find it worth a read.

Yours,

Dan

You'll need to remove the '#' from the start of any UCF line that you want to use. The '#' marks the line as a comment. So when you want to use these lines, just remove the '#'.

It's a shame, but one of the really annoying things about how Xilinx handles UCF files is that their tools will fail if you have a wire or pin defined that you aren't using. I say this is a shame, because it prevents someone from using the same UCF file for multiple projects: some that use one set of pins, some that use another. Instead, it forces you to have multiple UCF files, at least one for each project, and then to try to maintain them all together when your wiring changes.

At least, that's the reason why you may find lines commented out that you later determine you need. Because they weren't needed at first, they were commented in order to keep Xilinx's tools from failing. Now that you need them, you get to remove the '#' from the beginning of the line.

Hope that helps,

Dan

i tried this but the leds have not light on i dont know what is the problem can u check the ucf file if it correct for the switches can u check it please?

I'm not sure I can help much further. I don't have a Nexys board, so I can't verify what you are doing.

That said, if you are trying to use the port to turn LEDs on and off ... you are on the right path.

The only other suggestion I might have, if you are still struggling here is to disconnect your cable, and turn the master pins on and off. Measure them with a voltmeter and make certain that's working.

Also ... be aware, the PMOD connectors can be reversed. Getting VCC and GND confused with your data pins is probably not a good idea. Pay attention to how you have these set up.

Yours,

Dan

entity spi_loopback is
Generic (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '1'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2; -- prefetch lookahead cycles
SPI_2X_CLK_DIV : positive := 5 -- for a 100MHz sclk_i, yields a 10MHz SCK
);
Port(
----------------MASTER-----------------------
m_clk_i : IN std_logic;
m_rst_i : IN std_logic;
m_spi_ssel_o : OUT std_logic;
m_spi_sck_o : OUT std_logic;
m_spi_mosi_o : OUT std_logic;
m_spi_miso_i : IN std_logic;
m_di_req_o : OUT std_logic;
m_di_i : IN std_logic_vector(N-1 downto 0);
m_wren_i : IN std_logic;
m_do_valid_o : OUT std_logic;
m_do_o : OUT std_logic_vector(N-1 downto 0);





i asked someone he told that maybe u will not need the switches and leds in ur fpga
he told me to assign m_clk_i to the clock ,the m_rst_i to button and the ssel sck mosi miso to pmod connector
but he didnt knw where to set the m_di_i ,m_wren_i, m_do_valid_o , m_do_o. do u knw where those signals must be in ucf file

there is the ucf file for nexys3
http://www.xilinx.com/support/documentation/university/ISE-Teaching/HDL-Design/14x/Nexys3/Supporting%20Materials/Nexys3_Master.ucf

the project is to connect the spi master fpga with uartcable from pc and from spi master fpga we connect the spi slave from pmod connector and we connect another uartcable from spi slave to computer and then send from computer "hello" if it back it will works..

so i think just i need to locate the pmod connector in ucf file what do u think???!

That's right. All you need to locate in the UCF file, to get your transaction to work, are the SPI wires. The others may well be internal to the design.

Still ... I would find the LED's very useful while trying to learn whether or not I had the SPI cabling right ...

Dan