I want to use a CMOS sensor to capture immage and display this immage on PC, but now I got a problem, the CMOS type is MT9V022 and working under snap shot mode, main clock frequncy of CMOS has been configured at 25MHz which means the CMOS will sends one pixel data per 40ns, and data strem won't be stoped until one frame data transmitted over. When I use PS part receive those data through GPIO I found the reading speed of PS part is not fast enough and quite a lot of data is missing. Clock frequency of PS part is 666.66MHz which means PS part could run 26 assembly instructions per single pixel data, but GPIO needs more then 10 clock cycle to read one data and I also need time to write data to DDR, 40ns is not long enough. Is any one can tell me a better method to transmit data from PL part to PS. My platform is Xilinx Zynq 7010 series.
Many thanks

In this type of circumstance, you need to use a DMA peripheral to transfer your data. Otherwise, you have no guarantee that your program will always be the one running in the CPU. If it gets swapped out, your data transfer is lost.

Ideally, you want a hardware, not software, resource to transfer the incoming data from the camera into memory. More ideal, you want to transfer it to a video memory where the video driver will read it directly and place the results on the screen. That way the CPU never needs to touch anything with a real time requirement.

What I cannot tell you is whether or not the Zynq has the resources to do this. Sorry. Check the manual, and the Linux (or other O/S) distribution you have running on the ARMs. Linux has support for DMA transfers, but I don't know what support the Zynq has.

Yours,

Dan

use xilinx ip core VDMA

use xilinx ip core VDMA

I looked up the Xilinx VDMA core. It seems to provide high speed access between AXI4 and a memory, runnable from within your FPGA fabric. Does the Zynq FPGA have full access to the ARM main memory from the fabric?

If so, there are other solutions as well. I know I've posted one DMA controller that runs from a wishbone bus myself. It has both master and slave interfaces--master to control the transfer, slave to accept setup commands. I also know Olof has put together some DMA stream to wishbone interfaces, so these are quite doable.

Dan