I downloaded the g729a_codec in VHDL in Open Core site and I need some help for its implementation because I have all file (txt in VHDL lenguage) but I don't know how begin to use this code. I want to implemented in a Xilinx Kit with a Spartan 3AN for code voice.

I have a compact file wih the name g729a_codec_lastet.tar.gz, this compact file I downloaded in OpenCores site, in Projects, in Others G.729A Codec. Here You have an overview about the Codec and you can donwload the compact file. This compact file have some file, I want to use the txt file that are the vhdl file to implement the codec in a Xilinx kit with a Spartan 3AN.

Is this your first VHDL project? Or how familiar are you with building for FPGAs in general?

Dan

Hi MBF,

Browse the svn repo. The PDF (Appendix C) should be sufficient to get you started.
this will give you guidance on simulation (there's a dofile - *.do - Modelsim simulator command script - that probably facilitates test).

Given that you probably have background in the codec, this might help facilitate your understanding. FPGA design isn't easy in itself... but with hard work you can do this.

I would also consider your interfaces... how will you interface to the world using your Dev Kit? How would you interact with this to control and status your system. If you don't want to develop a UART you could get away with Chipscope (embedded logic analyzer) to monitor performance. Based on your initial question, and with deference to Dan's pointed and valid questions, I might be getting ahead of myself.

There are several tutorials from Xilinx and Altera that can get you started in FPGA design.
Good luck,
Jerry

Well, yes, is my first VHDL project and I have read some documents about this, but all are easy and simple example's description. I consider this project with codec G.729A is a little complex, it have many .txt file with VHDL source code and I don't kown started to prove this. I have ISE Design Suite 14.7 and a Xilinx Spartan 3AN Dev Kit and I want satart to do some test with this to kown if its (code G.729A) work or no.

Jerry I don't understand that about browse the svn repo, I need more datils for browse it, maybe you can give me the file's complete name.

Thanks Dan and Jerry, I wait for any help you can give me.

I apologize for my english.

My apologies if my question came out sounding condescending. It wasn't intended to be that, but rather a means to focus subsequent discussion.

One of the difficult parts of programming for an FPGA is deciding how to interact with that FPGA. Often, I have found that the support logic surrounding an FPGA algorithm can be just as difficult and challenging as the "main" FPGA algorithm itself. You might wish to treat this as a separate project in and of itself.

Years ago, working on a project, I built a fascinating infrastructure to help me with this sort of thing: The main project was a radio transmitter and receiver. The first thing I built to get this working was a means of communicating with the FPGA to read and write data from and to addresses on a "bus". One of these addresses was "special". When you wrote to this special address, it would clock all of the signal processing logic one tick. I could then go in and read, using the "bus", many (all?) of the internal signals that were a part of my algorithm. When I finally transitioned from a semi-automated signal processing system to a fully automated signal processing system, I already knew that everything worked as needed.

But my point here is---you need some kind of infrastructure to control the chip and get feedback from within the FPGA to tell you what is going on.

If you take the time to look at the projects I have here on OpenCores, you'll notice that the XuLA2-LX25 SoC project has this sort of approach. By writing special sequences to the USB-JTAG, the FPGA will decode these into wishbone bus commands within the FPGA, respond, and then return an encoded response across the JTAG. It's not the most efficient. In fact, it's pretty slow, but it does work. I've got other versions of the same thing running across a UART or even Digilent's parallel port interface (S6SoC project).

The reason for asking if this was your first project or not, is that usually this is a problem you solve early on in your first project--and a solution that you can cut copy and paste into subsequent projects, slowly improving along the way, until you interact with the FPGA in your favorite way.

Dan

Thanks a million Dan

But, what you advise me for start to do some test with this project if you know is my first project? I got the top level module (G729A_codec_sdp.vhd source code) and I copied it in a new project I did in ISE Project Navigator of ISE Design Suite 14.7 like a New Source and I run it but it had one error related with a library unit (work.G729A_ASIP_PKG.all)

I can't speak for the core you are working with (yet--I might look it up), however many (not all) of the cores on this site work well as components--not necessarily the entire design. As a component, you'll still need to make a top level. The top level you make will contain the actual connections to the wires on the board you'll be working with. I would also *highly* recommend that your top level include some debugging wires as well--at least until you know everything works. I've always been partial to an LED or two, but what I've been working with for debugging (recently) has been: 1) UART, 2) JTAG, or 3) Digilent's USB-8x parallel (DEPP) interface.

The only exception to this rule are those cores which are an entire design unto themselves. These ones will state what chip and board they were designed for. If you choose to use a different chip or board, then you'll likely need to redesign the top level, as mentioned above.

Again, this is why the comment about this being your first design. The structure you need to surround a core is typically the first design you build for your board. Get that working first, then place the core within it.

Hope this helps,

Dan