Hello, who can tell me the major differences between FPGA & ASIC? why a same RTL design could cost much more gates and run much slower while implemented in FPGA compared to ASIC? and what is the typical ratio in gates and speed? 3x. best regards. Z. ______________________________________ ÄúµÄÅóÓÑiamgfzhou£¬¸øÄú·¢À´ÁËÒ»Õźؿ¨£¡¹Û¿´>>( http://ecards.sina.com.cn/2000/2003-12-23/14394277464.swf ) ¼ÄÒ»Õźؿ¨¸øiamgfzhou( http://ecards.sina.com.cn ) ͨ¹ýÁËÁË°ÉÓëiamgfzhou½»Ì¸( http://668.sina.com.cn ) =================================================================== ½²Êö²ÊÉ«ÉÌÎñ¹ÊÊ£¬HPÃâ·ÑËÍÄãÈ¥Ñŵä (http://ad4.sina.com.cn/shc/zhuiyu_hprefresh.html)

iamgfzhou wrote:


Hi.

I think generally people in this group don't like to educate people in
basic areas like this. We've been getting a few too many students asking
for help with homework.

However, the actual difference in area is something I know a bit about,
and the answer surprises most engineers.

Basically, in the same process, pure logic will take up 40x to 100x more
area in an FPGA than in an ASIC. The difference is quite remarkable.
Power and speed, however, don't scale this badly.

FPGA vendors compensate with good marketting: Their advertised "system"
gate density is about 8x higher than the "real" gate density you can
actually put in the parts, where "real gates" are measured as number of
transistors used to implement the logic in a gate array / 4. "System"
gates include not just logic, but SRAM, advanced I/Os, microprocessors,
DLLs, etc, so it's not fair to compare them to logic gates, but the FPGA
sales guy wont tell you that on his next visit.

To be fair to the FPGA, the die area of a typical ASIC is not dominated
by logic, but by SRAM, and other diffused cores. The difference in
density between usable SRAM on an ASIC and an FPGA is only about 2x in
favor of ASICs, and only because ASICs can give you just the right
amount, and the right kind of SRAM, while FPGAs have fixed blocks of SRAM.

There are also many ASIC designs now days that are very highly pad
limited, so they are not able to take full advantage of their high logic
density.

Bill

Hi Bill, Yes, you really surprised me with your answer, saying FPGA-gates (as the vendors generally call it) are almost 40x to 100x the ASIC gates. I work on pre-silicon-prototyping of a fairly large SoC. Our design in no way matches the general guidelines for FPGA-based designs. But my observation was that no. of FPGA gates = (4 to 5 times) the no. of ASIC gates. that is, for a 1 million gate design, I need atleast a 4-million gate FPGA device. I request the senior people in the list to correct me if necessary. We generally matched logic to logic and memory capacity to memory available in the FPGA. Xilinx, the primary FPGA vendor in the world, talks about the number of Slices (Virtex-E devices) and BlockRAMs separately and gives its equivalent gate count based on an industry standard design fitting into it (excluding the memory part, o'coz). Hope I am clear in what I wanted to express here. I would feel much better if my knowledge is either confirmed or contradicted by any of the senior members of the list. Regards, -Ramakrishna Bill Cox bill at viasic.com> wrote: iamgfzhou wrote: Hi. I think generally people in this group don't like to educate people in basic areas like this. We've been getting a few too many students asking for help with homework. However, the actual difference in area is something I know a bit about, and the answer surprises most engineers. Basically, in the same process, pure logic will take up 40x to 100x more area in an FPGA than in an ASIC. The difference is quite remarkable. Power and speed, however, don't scale this badly. FPGA vendors compensate with good marketting: Their advertised "system" gate density is about 8x higher than the "real" gate density you can actually put in the parts, where "real gates" are measured as number of transistors used to implement the logic in a gate array / 4. "System" gates include not just logic, but SRAM, advanced I/Os, microprocessors, DLLs, etc, so it's not fair to compare them to logic gates, but the FPGA sales guy wont tell you that on his next visit. To be fair to the FPGA, the die area of a typical ASIC is not dominated by logic, but by SRAM, and other diffused cores. The difference in density between usable SRAM on an ASIC and an FPGA is only about 2x in favor of ASICs, and only because ASICs can give you just the right amount, and the right kind of SRAM, while FPGAs have fixed blocks of SRAM. There are also many ASIC designs now days that are very highly pad limited, so they are not able to take full advantage of their high logic density. Bill _______________________________________________ http://www.opencores.org/mailman/listinfo/cores --------------------------------- Do you Yahoo!? Yahoo! Hotjobs: Enter the "Signing Bonus" Sweepstakes -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20040106/a6176609/attachment.htm

Hi Bill,

Yes, you really surprised me with your answer, saying FPGA-gates (as the
vendors generally call it) are almost 40x to 100x the ASIC gates. I work on
pre-silicon-prototyping of a fairly large SoC. Our design in no way matches
the general guidelines for FPGA-based designs. But my observation was that
no. of FPGA gates = (4 to 5 times) the no. of ASIC gates. that is, for a 1
million gate design, I need atleast a 4-million gate FPGA device. I request
the senior people in the list to correct me if necessary.

[Deepu C John]
this info is not from my experience.. got from some discussion lists /boards ) We generally matched logic to logic and memory capacity to memory available in the FPGA. Xilinx, the primary FPGA vendor in the world, talks about the number of Slices (Virtex-E devices) and BlockRAMs separately and gives its equivalent gate count based on an industry standard design fitting into it (excluding the memory part, o'coz). Hope I am clear in what I wanted to express here. I would feel much better if my knowledge is either confirmed or contradicted by any of the senior members of the list. Regards, -Ramakrishna Bill Cox bill at viasic.com> wrote: iamgfzhou wrote:
implemented in FPGA compared to ASIC? and what is the typical ratio in gates
and speed?
http://ecards.sina.com.cn/2000/2003-12-23/14394277464.swf ) (http://ad4.sina.com.cn/shc/zhuiyu_hprefresh.html) Hi. I think generally people in this group don't like to educate people in basic areas like this. We've been getting a few too many students asking for help with homework. However, the actual difference in area is something I know a bit about, and the answer surprises most engineers. Basically, in the same process, pure logic will take up 40x to 100x more area in an FPGA than in an ASIC. The difference is quite remarkable. Power and speed, however, don't scale this badly. FPGA vendors compensate with good marketting: Their advertised "system" gate density is about 8x higher than the "real" gate density you can actually put in the parts, where "real gates" are measured as number of transistors used to implement the logic in a gate array / 4. "System" gates include not just logic, but SRAM, advanced I/Os, microprocessors, DLLs, etc, so it's not fair to compare them to logic gates, but the FPGA sales guy wont tell you that on his next visit. To be fair to the FPGA, the die area of a typical ASIC is not dominated by logic, but by SRAM, and other diffused cores. The difference in density between usable SRAM on an ASIC and an FPGA is only about 2x in favor of ASICs, and only because ASICs can give you just the right amount, and the right kind of SRAM, while FPGAs have fixed blocks of SRAM. There are also many ASIC designs now days that are very highly pad limited, so they are not able to take full advantage of their high logic density. Bill _______________________________________________ http://www.opencores.org/mailman/listinfo/cores _____ Do you Yahoo!? Yahoo! Hotjobs: Enter http://pa.yahoo.com/*http://us.rd.yahoo.com/hotjobs/mail_footer_email/evt=2 1482/*http://hotjobs.sweepstakes.yahoo.com/signingbonus> the "Signing Bonus" Sweepstakes -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20040106/35bc2993/attachment.htm

You see different numbers to move from FPGA gates to ASIC gates. It basically depends on the FPGA you use. The official number from Xilinx is 6FPGA gates to 1 ASIC gate. It also depends on whether you calculate the flipflops and LUTS together, or separate. I tend to count flipflops and LUTS separate; using 8gates for the flipflops and a variable number (depending on the FPGA) for the LUTS. Most modern FPGAs –think Virtex and descendants, or Flex/Apex style FPGAs- scale to about 2-3 gates per LUT. And then there’s the memory of course. You should also read Bill’s text carefully. He states that the same logic occupies approx. 40-100x the area in an FPGA compared to an ASIC. Area being actual silicon, not gates. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of Deepu C John Sent: Tuesday, January 06, 2004 10:19 AM To: 'Discussion list about free open source IP cores' Subject: RE: [oc] The difference between FPGA and ASIC Hi Bill, Yes, you really surprised me with your answer, saying FPGA-gates (as the vendors generally call it) are almost 40x to 100x the ASIC gates. I work on pre-silicon-prototyping of a fairly large SoC. Our design in no way matches the general guidelines for FPGA-based designs. But my observation was that no. of FPGA gates = (4 to 5 times) the no. of ASIC gates. that is, for a 1 million gate design, I need atleast a 4-million gate FPGA device. I request the senior people in the list to correct me if necessary. [Deepu C John] (NOTE: this info is not from my experience.. got from some discussion lists /boards ) We generally matched logic to logic and memory capacity to memory available in the FPGA. Xilinx, the primary FPGA vendor in the world, talks about the number of Slices (Virtex-E devices) and BlockRAMs separately and gives its equivalent gate count based on an industry standard design fitting into it (excluding the memory part, o'coz). Hope I am clear in what I wanted to express here. I would feel much better if my knowledge is either confirmed or contradicted by any of the senior members of the list. Regards, -Ramakrishna Bill Cox bill at viasic.com> wrote: iamgfzhou wrote:
while implemented in FPGA compared to ASIC? and what is the typical
ratio in gates and speed?
http://ecards.sina.com.cn/2000/2003-12-23/14394277464.swf ) (http://ad4.sina.com.cn/shc/zhuiyu_hprefresh.html) Hi. I think generally people in this group don't like to educate people in basic areas like this. We've been getting a few too many students asking for help with homework. However, the actual difference in area is something I know a bit about, and the answer surprises most engineers. Basically, in the same process, pure logic will take up 40x to 100x more area in an FPGA than in an ASIC. The difference is quite remarkable. Power and speed, however, don't scale this badly. FPGA vendors compensate with good marketting: Their advertised "system" gate density is about 8x higher than the "real" gate density you can actually put in the parts, where "real gates" are measured as number of transistors used to implement the logic in a gate array / 4. "System" gates include not just logic, but SRAM, advanced I/Os, microprocessors, DLLs, etc, so it's not fair to compare them to logic gates, but the FPGA sales guy wont tell you that on his next visit. To be fair to the FPGA, the die area of a typical ASIC is not dominated by logic, but by SRAM, and other diffused cores. The difference in density between usable SRAM on an ASIC and an FPGA is only about 2x in favor of ASICs, and only because ASICs can give you just the right amount, and the right kind of SRAM, while FPGAs have fixed blocks of SRAM. There are also many ASIC designs now days that are very highly pad limited, so they are not able to take full advantage of their high logic density. Bill _______________________________________________ http://www.opencores.org/mailman/listinfo/cores _____ Do you Yahoo!? Yahoo! Hotjobs: Enter http://pa.yahoo.com/*http:/us.rd.yahoo.com/hotjobs/mail_footer_email/ev t=21482/*http:/hotjobs.sweepstakes.yahoo.com/signingbonus> the "Signing Bonus" Sweepstakes -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20040106/f4224459/attachment.htm

Richard Herveille wrote:


Hi, Richard.

I should have been a bit more clear, so I'll restate it: The same
Verilog RTL circuit (consisting of just logic gates) will take 40x to
100x more space on a die when implemented in an FPGA fabric rather than
an ASIC fabric. This has nothing to do with the ratio of "system" gates
vs gate array logic gates.

Everything people said about FPGA-to-ASIC gate ratios are correct. I can
add that I carefully measured the ratio myself for a Virtex device vs an
AMI gate array using several RTL netlists, including Sun's PicoJava
design. I used Synplicity synthesis to map to both devices, and compared
the reported number of transistors/4 from the AMI run to the number of
slices reported from the Virtex run.

The ratio was 8.1. An "official" ratio of 6 is just honest enough to be
convincing, but not quite the truth. The purpose of marketting is to
increase profits. Xilinx has good marketting.

It turns out that the ratio of claimed gate density in FPGAs vs real
gate density has been climbing since the introduction of the first FPGA.
In the early 90's the ratio was close to 2.

There's a slightly funny story from my days working at QuickLogic. We
didn't have a marketting group, so naturally the engineers that make up
most of our company decided to be honest about gate density. We called
our 4K gate device a 4K gate device, and it was. Our team thought that
FPGA users would react positively to our honest marketting. It didn't
work. For years, Xilinx and Altera sales teams trashed our teams using
simple inflated gate claims. In the mid-90's, we released a new product
line that was virtually identical to our last one, but shrunk down to a
smaller process. At the same time, we multiplied our claimed gates by
2.6! Sales picked up, our company went IPO, and the user's never seemed
to notice our re-labelling.

Bill

than

gates


Right, exactly what I said in my last lines.


can

an

compared

be


Now you're talking about a gate array. For a std.cell asic the
difference is bigger. AMI used to have tables listing the GateArray and
ASIC gates numbers for all kinds of FPGAs. However they removed those.
Quite a shame I think. They were very useful.


FPGA.


Correct.
Not to mention that the part numbers started to being numbered on a
sequential range, instead of actual density.


up

product

a

seemed


Well what do you want?
We are all sheep, beeeh.

Richard

>>>>> "Bill" == Bill Cox bill at viasic.com> writes: ... Bill> There's a slightly funny story from my days working at Bill> QuickLogic. We didn't have a marketting group, so naturally the Bill> engineers that make up most of our company decided to be honest Bill> about gate density. We called our 4K gate device a 4K gate device, Bill> and it was. Our team thought that FPGA users would react Bill> positively to our honest marketting. It didn't work. For years, Bill> Xilinx and Altera sales teams trashed our teams using simple Bill> inflated gate claims. In the mid-90's, we released a new product Bill> line that was virtually identical to our last one, but shrunk down Bill> to a smaller process. At the same time, we multiplied our claimed Bill> gates by 2.6! Sales picked up, our company went IPO, and the Bill> user's never seemed to notice our re-labelling. At least I wiped my eyes when I compared QL I/II/III families and noted the diifference. Comparing the numbers of CLBs in a Xilinx XC2S200 and XC3S200 is also eye opening... With my limited experience, the Quicklogic Supercell however seem less capable to me compared to the Altera LE or Xilinx CLB, as the Latches have no explicit Clock Enable and the Cell has no provision for the inter cell carry chains. Bye -- Uwe Bonnes bon at elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

With my limited experience, the Quicklogic Supercell however seem less
capable to me compared to the Altera LE or Xilinx CLB, as the Latches have
no explicit Clock Enable and the Cell has no provision for the inter cell
carry chains.