Hi,
I wanted to make the input synchronization (using 3 flip flops) logic generic using function/procedure in a package.

Is it possible ?

Lots of things are possible. However, I'm not certain from your description what you wish to do.
Can you be more specific?

Dan

Hi Dan,

Like an adder, sub-tractor, data type conversion functions etc which can be written as a function (in a package) and call the function across different modules. I wanted to do input synchronization circuit also using a function/procedure, so that I can call this function where ever there is a CDC signal.

My understanding is functions/procedure (in VHDL) generates combinational circuit not sequential, so in any way can we make input synchronization circuit using function/Procedure ??


Thank you,
Purushotham.

Purushotham,

Yes, it is possible to accept inputs into a VHDL module, together with a clock, and to produce outputs a short time later synchronous with that clock. These outputs can be adds, subtracts, multiplies, even divides, sines and cosines. You might find some fascinating examples of this among the arithmetic projects on this site.

The idea behind "OpenCores" is that each of these "Cores" can be a component of another design. I know among my own designs, I tend to use "cores" among many of my designs: For example, once I build a sine/cosine generator, I really don't intend to rebuild it every time I need it again.

Yes, it is true that all logic is parallel/combinatorial within a VHDL or Verilog construct. However, this "parallel" logic can be made to act on a clock, and thus to do sequential things by means of a state machine. (You might wish to google "state machine" ...)

My guess is that just about every core available on this site uses some kind of state machine. The classic example would be the soft-core CPU's available under Projects/Processors, or even Projects/System on a Chip. As I'm sure you are familiar that CPU's can handle sequential logic, no? So then, if VHDL can be used to describe a CPU that can handle sequential logic, then an FPGA (running a soft CPU) can handle sequential logic as well. If you want a simpler example, you might wish to look up a UART controller--you'll also find several of those on this site. Each of those implements a state machine internal to it as well.

Hope this helps. If not, please expand and explain on your question some more,

Dan