I am trying to understand the implementation code for cache, in cache.vhd file. I do not understand how the cache is implemented to be mapping only 2MB of the DDR memory. In the file, the following code is written:

if state = STATE_IDLE then --check if next access in cached range
cache_address if address_next(30 downto 21) = "0010000000" then --first 2MB of DDR

I don't understand how does the last line ensure that we only use 2MB of DDR? What is the use of this last line?

Which file from which core are you referencing?

Dan

I have attached the file I am referring to, it is the code for the cache controller. Also please explain, what is the difference between cache_address and cache_ram_address in this code?

Sorry somehow the file didn't attach. I am referring to the cache controller implementation, cache.vhd for the plasma processor.