Hi,

currently I am trying to use this sensor:
https://www.sparkfun.com/products/11050 (DS18B20 temperature sensor)

with an FPGA using this core:
http://opencores.org/project,sockit_owm (small 1-wire master)

I have two seperate parts that I need help with, first; I am writing my project in VHDL and the core is in Verilog so I am unsure if I am modifying the correct parts of the core.
And second, I am having trouble understanding how the core is actually used.

To explain what I have done so far I have taken the sockit_owm.v file and imported it into my Vivado project and modified the contents. First I modified the file to work with a 50Mhz clock, switched off overdrive and changed the data bus width to 8. I did this because the commands sent to the sensor are 8 bits, but the temperature data received back is 12 bits. So my first questions is how do I manage this? Do I make the bus width 12 and pad the commands with 4 bits?

After modifying the file I tried to write a wrapper around it in VHDL so that I can send the skip_rom command to the temperature sensor and then read the sketchpad. So my second question is how do I actually use the sockit_owm.v to send and receive data. The inputs to the module are read/write enable and read/write data, so my first guess was to put write enable
I have been going round in circles with this for a few days now, and I'm pretty new to VHDL so this is really frustrating.

Any help would be appreciated. I did a search on the site but it turned up over 8 pages of results so I couldn't find if this had been asked before.

Best
Tom

This is a bit late, but you might try the one_wire_master core. It will handle the entire 18b20 interface for you including initializing one or more parts on the one wire bus and output the temps. Or you can use just the on_wire interface and control the bus with your own logic.