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hdl designer xilinx flow with verilog
by Unknown on Jun 10, 2005 |
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Whenever I use hdldesigner and a core that uses a defines file, When I
go to compile it says "cannot open 'include blah.v" or something like that. I've had this happen to me before, and my workaround was to just copy contents of blah.v and replace the include file. But thats really ugly for this paticular core so I'm trying to find out the proper way to do this. Thanks in advance. ** Error: C:\hds_projects\ION2/Wishbone_RS232/hdl/uart_rfifo.v(151): Cannot open `include file "uart_defines.v". Jamey |
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hdl designer xilinx flow with verilog
by Unknown on Jun 21, 2005 |
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Short version: Don't use ISE to compile your files
ISE requires all include files to be correct relative to where you started it from. So you would need to change every include to: `include "my/relative/path/include.vh" Theoretically there's an +incdir type directive so you don't have to do that, but it's simpler to just create a command-line script and use XST from the command line. xst -ifn compile.scr compile.scr: run -ifn compile.list -ofn my_design.ngc -top my_design_top -keep_hierarchy Yes -ofmt NGC -uc my_constraints.xcf -p xc2VP7-FF672-6 -opt_mode Speed -opt_level 2 - Guy |
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