hi,
i had developed a simple i2c bus master in VHDL and was using I2C
slave verilog code taht was available over here for the purpose of
testing. When i am giving the start, and the address of the slave,
the
slave is not generating the acknowledgement bit. Since i donot know
verilog, i couldnot figureout why such problem came up.
Shouldn't the slave send an acknowledgement bit after the master
addresses it ? If yes, can anybody let me know it the verilog slave
code available over here would respond with the acknowledement bit
or
not ?
Also let me know if there is slave module for simualtion in VHDL
anywhere on the web.
Thanking you all in advance
regards,
Vikas