Hi

Question about Wishbone:
I could not find a clear statement if mixed read/write cycles should be allowed.
The only pointer in this direction is the existence of the RMW-cycle.

However, is there a clear idea if a single master could change WE while CYC is active?

Thanks and best regards,
emanuel

I just searched the B4 specification for any information regarding your request. What I found was rather vague. The closest I have to an answer is to note that the specification discusses "read cycles" and "write cycles", and that a cycle would begin when the cycle line (CYC) is raised and lowered when the cycle line is lowered.

This answer is certainly unsatisfactory for RMW cycles which need to keep the CYC line high. For this reason alone, It makes sense that a bus cycle needs to be able to include both read and write requests, and therefore that my reading above is insufficient.

I will say this, the Formal verification properties I use to verify a WB/B4(pipelined) interface require that 1) there needs to be at least one-clock cycle between direction changes, and 2) that any direction change can only take place when nothing is outstanding. This has fit my needs quite well, since these are the only reasons why any of my own bus transactions would ever change direction.

From the perspectives of the slaves that I have written, most of them don't care.

Not sure if this helps, but it was what came to mind, Dan