Hello,

How feasible it is to design a 4-core cpu on a FPGA Spartan 3E. I don't want to design something complicated, but a processor to test a few algorithms, designed for embedded, how fast they can run on FPGA...

Thank you.

Yes you can make a nice 4 core processor (easy if it's a simple processor).

The Propeller 2, for example, is a type of 8 core processor that's implemented in 301,000 logic elements and 12.2 Mbit SRAM.

Generally, it’s very feasible for a four-core system unless you’re using a really small part. (is the part a 500E or larger?) It depends on how large of a part you can use and how large the cpu is. It also depends on how the cpu’s are interconnected. Is it using shared ram? Serial or parallel connections? The interconnection may use just as many resources as the cpu cores. Cpu size varies quite a bit. Something like the pico-blaze is very resource friendly, but also limited in what it can do. I can give a quick example as a guesstimate a small cpu might only be 500-600 LUTs. If serial ports are used to interconnect the cpu’s say 500-600 LUTs more for 4 ports per cpu. I don’t think it’s very likely that 4 cpu system could be fit into a XC3S100E for instance.
I have put together a 56-core system before but that was in a largish FPGA (7a200t), and a smaller dual-core system in an XC3S1000 with a lot of other peripherals.

Thank you for your answers. I am looking it....

I want to assign the load to each core, according to a algorithm I have designed. Is it feasible to control each core?

I use 500E FPGA. Can I just "copy-paste" the pico-blaze 1-core processor 4 times to make it 4-core and of course configure it, to work properly?

I recommend you for trying leros https://opencores.org/projects/leros

Something else. How can I find what elements of a processor, does an algorithm take care in order to assign (in multi-core processors) the load to each core?

Thank you...

Hello, I have been designing a RISC and clockless processor for some years now. It is still in preliminary design phase.

The design is multi-core and I want to use processor-provided partitioning facility to limit the number of times a thread is run.

I welcome you to participate in my project. The OC page is ( http://www.opencores.org/projects/taar ).

What elements are required for a 4-core CPU system, so that the cores can control the others respectively?

I was thinking about that earlier, and I think I would go with the debug port. As long as one core has access to the debugging ports of the other three, it should be able to start, stop, and adjust them. What would this access look like? Something necessary to read internal registers, change internal registers, and to start, stop, reset, and step the CPU.

Beyond that, the choice of how to control a sibling processor is about as wide open as the instruction set and implementation of the sibling processors. You get to design how you want it to behave.

Be very aware of the bus and bus issues. Unless you do some sort of complicated caching scheme, or allocating block RAM to each core, you might be disappointed that the speed of your four cores are limited by the speed of the single access to memory.

Dan