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SIMD
by firas2010 on Feb 12, 2020
firas2010
Posts: 1
Joined: Feb 9, 2020
Last seen: Feb 17, 2020
Hi all,

I want to implement SIMD architecture on FPGA. I am new in this field and try finding a software for simulating and implementing SIMD architecture. Can you please guide me about this? I really appreciate your help.

Kind Regards
Firas
RE: SIMD
by PabloMack on Mar 27, 2020
PabloMack
Posts: 1
Joined: May 31, 2019
Last seen: Mar 28, 2020
SIMD is really just what it stands for. These instructions do multiple operations instead of just one in parallel. For sake of generality, a vector is just the simplest form of an array. So when I talk about arrays, I am including vectors. There are two reasons why you might want to have SIMD:

1. Simplify coding by handing multiple operations of the same type in the same instruction stream.
2. To speed up array and vector operations.

The only differences between array and scalar operations are:

1. You have to have "registers" that hold two or more values at the same time. These can be special memory units inside the CPU or even just data structures in memory that are treated as such. SIMD is really more of an instruction encoding method than it is a hardware architecture, though it is usually implemented in hardware for speed.

2. You will either have to have a separate set of status flags for each element, limit yourself to operations that don't need them or use the operations for purposes that don't care about the loss of range and precision information when overflows and such happen.

For example, you might use saturating adds and not support regular adds that roll over. If you did use adds that roll over then the results should be acceptable as they are because SIMD processors normally don't deal with the conditions brought about in the processing of individual array elements. To do so would defeat the effort to have "Single Instruction" handling of the data structure from the start. There are uses for adds that don't care about data loss due to rollovers like check sums. These are used for error checking so the results don't have to be mathematically precise in the applications in which they are normally used.

I have been developing a general purpose SIMD architecture for a long time so it is one of my favorite subjects. It is called "The ϕ System". It has three parts and these are ϕPPL, ϕEngine and ϕOS. They all use full Unicode for their software development tools. ϕPPL is the Parallel Programming Language that generates SIMD instructions implicitly and easily. ϕEngine is a 64-bit CPU architecture that implements it in hardware. ϕOS is an operating system that is written mostly in ϕPPL. Together they solve a lot of problems in the computer industry that seem to just linger on forever elsewhere "...just because that's the way it has always been done" and "because that is what the big corporate giants said we have to use".
RE: SIMD
by Agner on Apr 11, 2020
Agner
Posts: 9
Joined: Mar 23, 2016
Last seen: May 29, 2020
I am working on a new core and a new ISA with variable length SIMD registers.

I have discussed it here four years ago: https://opencores.org/forum/Cores/0/5762

I will not have any status registers. Floating point errors will be coded as NAN payloads in each vector element. Integer overflow will optionally be indicated in an extra vector element. No instruction will have more than one register output.

Progress has been slow because I have been busy on other projects, but now I am beginning to make a soft core. In the meantime I have updated the ISA specification and ABI standard and made a binary toolchain: high level assembler, disassembler, linker, library manager, and emulator. It is all documented on https://www.forwardcom.info

I will start a project here on opencores soon with the name ForwardCom
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