Dear all.

I am developing a new open vector processor named ForwardCom with a lot of interesting new features. All specifications, ABI, and binary tools are in place (see www.forwardcom.info). Now I have started to develop a soft core for an Artix-7 FPGA.

I am thinking about how to coordinate the processing between the different stages in the pipeline. My ideas of how to do this are described below. I want to know if I am doing the right thing or if there is a better way of doing this. I don't want to reinvent the wheel if there is a good standard solution already.

OK, so here is my idea: Each stage in the pipeline is a module with the following inputs and outputs:

* stall_in: Tells the module for this stage to keep its output data because the rest of the pipeline is unable to receive it in the next clock cycle.

* stall_out: This module is unable to receive a new instruction in the next clock cycle because it is waiting for an operand or it is busy with a task that takes multiple clock cycles in the same stage.

* idle_out: This module contains a pipeline bubble or anything else that requires no action.

* ready_out: This module has an instruction ready for the next pipeline stage.

* ready_in: Connected to the ready_out of the preceding pipeline stage.

* and of course inputs and outputs of an instruction and its data.

The stall_out signal is not registered, unlike other outputs, because it is difficult to predict a stall in a future clock cycle. The stall_out must be implemented with simple logic (1-2 LUTs?) so that it is ready early in the clock cycle.

It would be logical to propagate the stall signal backwards through the pipeline, but this would be too slow for stalling the entire pipeline in a single clock cycle. Instead, I will make a look-ahead logic in the top level module. This logic will give each pipeline stage a stall_in signal if any later stage in the pipeline generates a stall_out signal and no stage in-between has an idle_out.

Is this a good way of doing it?

Yes, there is a good way of handling this. It's called a Skidbuffer. For a more generalized discussion of pipeline handshaking, see this article.

Dan