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JPEG2000 core
by omerc100 on Aug 28, 2020 |
omerc100
Posts: 1 Joined: Oct 17, 2018 Last seen: Jun 19, 2022 |
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Please can someone upload JPEG2000 project in VHDL/Verilog for image compression on FPGA..?
Thanks a lot |
![no use](https://cdn.opencores.org/img/pils_lt.png)
![no use](https://cdn.opencores.org/img/pil_lt.png)
![no use](https://cdn.opencores.org/img/pil_rt.png)
![no use](https://cdn.opencores.org/img/pils_rt.png)