Hi,

I am trying to reproduce a ZX81 using a Spartan 7 Xilinx FPGA.
I use a t80 in replacement of the z80.
For RTL simulation the design works fine. The result is as expected.

However, when performing post-synthetisis simulation, it does not work anymore.
I have spent a lot of time to understand what can be the diffrence between RTL and post-synthetisis results.
The issue appears when Z80 instruction "DEC HL" is executed. Sometimes, HL is badly decremented.
In the attach example (bottom picture), HL moves from 0x408c to 0x808b instead of 0x408b. However, time to time it works (see top picture).

My conclusion is that the issue is related to this part inside T80.vhd VHDL:
ID16 signed(RegBusA) - 1 when IncDec_16(3) = '1' else signed(RegBusA) + 1

In some case it does not seems to work.
As you may seen inside attached picture, RegBusA input value is ok but ID16 output value is wrong.
Did you already encounter this kind of problem ?
Is it a Vivado issue ?
May it be replaced by something else ?

Thanks for your help,

Yann

I had a case in a project I was working on that seems a bit similar. It turned out to be bad ram on the workstation. There was a bit error that cropped up in simulation sometimes but not others. I was able to prove it was a workstation bit error and get around it by recoding part of the project as triple-mode redundant (TMR). Since the simulation had to run the TMR it adjusted accordingly.
I would try running a ram tester on the workstation.