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the work entity in Quartus
by monahanz on Oct 31, 2021 |
monahanz
Posts: 1 Joined: Aug 25, 2018 Last seen: Mar 22, 2024 |
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I have been using .vhd files from here with good success in Intel's Quartus.
However in many cases I reach a roadblock. In all such cases there are multiple files to compile. For example:- I would like to make a .bdf module from the “Simple UART for FPGA” by Jakub Cabal. The UART.vhd root file has at the start use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.MATH_REAL.ALL; all of which are fine with Quartus. But down a few lines there is:- os_clk_divider_i : entity work.UART_CLK_DIV generic map( DIV_MAX_VAL => OS_CLK_DIV_VAL, DIV_MARK_POS => OS_CLK_DIV_VAL-1 ) I get this a lot. Quartus gets hung up on finding the entity “work” What do I need to add. Thanks in advance John |
RE: the work entity in Quartus
by fier on Nov 3, 2021 |
fier
Posts: 1 Joined: Mar 30, 2016 Last seen: Nov 4, 2021 |
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Frank Ieromnimom (IDE, Greece): RE: the work entity in QUARTUS
The Quartus tool is missing the entity UART_CLK_DIV, which should be compiled into the work library, where the rest of the files for the UART should be compiled as well. |
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