Hello all, I would just like to start out by commending you and this site for a job well done. I am interested in starting a project on here to create a standard 5 stage pipeline MIPS core from the ground up. I know it's probably been beaten to death, but it's what I know. Before I start this, however, I have a few questions. I know VHDL but it seems as though most projects on here are Verilog. Is there a reason for this? I have been writing my VHDL in Symphony EDA (Free version) but it is a crippled, reduced speed version. I was wondering if there was anything better that you can recommend. I would like to work in Linux, but if I must I can work in Windows. Are there any recommended environments out there? I have found FreeHDL [1], but it seems incomplete from what I gather. Also, does anyone have any guides/comments/tips for me before I start, either MIPS related or general core design? I plan on this being a work in progress for a while and I will probably only submit a project when this becomes somewhat substantial. Thanks, Kevin Lynch [1] http://www.freehdl.seul.org/index.html

On 7/25/05, kevin klynch at gmail.com> wrote:

Some start-of-project questions:
* What would this accomplish which has not been done by the existing
MIPS cores? If it's to write it in VHDL instead of Verilog, what
about porting an existing core to VHDL?
* What is your plan for dealing with MIPS legal issues?



I will skip my gut reaction to why not to code in VHDL. There are a
substantial number of VHDL cores on the site; if there are more
Verilog cores recently, it may be because there are more free
simulators available for Verilog now.

Other recommendations: MIPS related: If you don't have a copy of
Hennesey and Patterson, get one. On general core design, don't use
technology-specific components, and take RAMs and other components
which you know will have to be hardened and create generic models for
them.

- Guy

Le lundi 25 Juillet 2005 20:28, kevin a écrit :



try ghdl from ghdl.free.fr

Hi,



If you want to work on a MIPS core.. I find the book on the R2000 architecture
by Kane to be really useful.. It has all the necessary details...

Verilog is supposed to be slightly lower level than VHDL and produces better results than VHDL.. VHDL is often taught in schools but Verilog is quite often used in industry... That being said, if you're interested to learn, you could do a conversion from Verilog to VHDL or vice-versa.. It'll give you a chance to learn and compare both languages..

There are several verilog software.. icarus and cver comes to mind.. don't
know any vhdl ones though.. Alternatively, you could use say, the Xilinx ISE
(which has a free linux version as well).. It'll happily do both languages..



Yes... having done a few processor designs.. Besides Kane, the book on
computer architecture from H&P as suggested by another post.. Plus plenty of
paper... Get your design down on paper (down to the last flip-flop) before
you even start with a single line of code... It will save you a lot more
time...

Another advice, study the codes from the different chips available online..
I've always found it much faster to learn from code...



Good luck!!!

cheers..

--
with metta,
Shawn Tan

I'm using Xilinx Webpack 7.1i They have a free version avaliable from their website www.xilinx.com and don't forget to donwload Chipscope aswell they too have a free non-comercial version. The Webpack is only limited in code size upto 200000 gates I think and certain of the Virtex 4 chips will not compile. Otherwise to get statred it's great! Hope this helps. Quintin Immelman ---------- Original Message ---------------------------------- From: Nicolas Boulay nico at seul.org> Reply-To: Discussion list about free open source IP cores cores at opencores.org> Date: Mon, 25 Jul 2005 21:16:44 +0200





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Most FPGA companies offer free tools for their FPGAs. ISE Webpack is not really limited in terms of gate count but it does lack support for most Virtex FPGAs (no support for CoreGen so no MGT, no PPC, no Ethernet MACs, etc.) and the largest Spartan 2/3 family members. Although Webpack does not have an explicit gate count limit, there is an implicit one in the form of the largest supported device which is the XC3S1500 at the moment. Some (at least Xilinx and Altera) also have special arrangements with Mentor to provide free Modelsim. From the WebPack FAQ, it seems XE-III does not have a complexity limit but simulation performance is increasingly artificially degraded as the code exceeds 10k total statements. Post-PAR simulation with timings for a nearly full 1.5M gates FPGA would very likely be an exercise in patience. (RTL simulations for a ~85% full XC2VP40 with Modelsim SE are already fairly slow, PAR+timings on XE of the same would probably take forever.) It is nice to have free stuff, all I need now is low-cost FPGAs (and related tools) featuring Multi-Gigabit Transceivers. With everything is going serial, interfacing PCs and PC-style components is becoming a major chore: external PHYs cost $10 + ~40 pins each, are somewhat elusive and supersizing the package to accomodate the external PHYs probably adds more cost than integrating quad MGTs. ----- Original Message ----- From: MEDS INTERNATIONAL Quintin Immelmanquintin at m...> To: Date: Thu Jul 28 11:21:42 CEST 2005 Subject: [oc] Project Beginnings

According to this, WebPACK isn't limited to 200k gate chips: http://www.xilinx.com/xlnx/xebiz/designResources/contentContainer.jsp?sSecondaryNavPick=Design+Tools&iLanguageID=1&key=webpack_faq&sGlobalNavPick=PRODUCTS&BV_SessionID=@@@@1071146309.1122755705@@@@&BV_EngineID=cccdaddfellemiecefeceihdffhdfjf.0#1b