Sir/Madam I am new in FPGA . I took to implement FIR in FPGA . I decided Direct form fir so blocks are symmetric and easy to add taps, Konstant Coefficient Multiplier , decimators and Delays. I 've written code in VHDL and simulated in modelsim and synthesised in Xilinx ISE5.1 . I chose spartan 2 144pin FPGA. As i havent downloaded it yet to any FPGA so my question is that whether I need more blocks to be made (e.g. memory interfacing, as any data voice or image will be firstly stored in some ram , so is RAM present in FPGA board?. what should i look forward to , so that I can test my FIR filter with reeal set of datas. shresthakumar at gmail.com