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DDR SDRAM controller by Unknown on Aug 15, 2006			Not available!
Can someone please let me know where the DDR SDRAM controller code is located? I can't find it in the website anymore. Strange, ANy comments on this core's performance comparing to Xilinx Virtex4 ones is appreciated!!! Thanks, Roger ----- Original Message ----- From: xjf77 at yahoo.com<<A HREF="http://www.opencores.org/mailman/listinfo/cores">xjf77 at y...</A>> To: Date: Fri Aug 26 15:12:38 CEST 2005 Subject: [oc] DDR SDRAM controller [q] Dear Cargnini, I would like to discuss some problems with regards to MIG007. I would like to generate the ddr sdram controller for for ML310 circuit onboard 256MB DIMMs. I have the following problems. 1. MIG007 currently support only unbuffered DDR SDRAM. While my onboard DIMMs is registered, dose this affects the operation? 2. In my case, I am wondering which memory type I can select (component or dimms?). If select DIMMs, then SDRAM part data width is restricted to 64/72 bits. While I see the EDK plb-ddr sdram for ML310 use only 32 bits of DDR SDRAM data pins. How dose it come? Feel puzzled on it. 3. MIG007, as Anna said, seems to be not compatible with the real circuit board pin out constraints, i.e., some real DQS pins are not allowed to be allocated as DQS pin in MIG007-Pin Editor. It's better to neglect the Pin Editor using my own ucf file, I think. Otherwise we have to manually modify the generated ucf file to adapt to the board pin connection. That's it! Thanks a lot in advace. regards, Jeff ----- Original Message ----- From: LuÃs VitÃ³rio Cargnini<cargnini at m...> To: Date: Thu Aug 11 06:15:45 CEST 2005 Subject: [oc] DDR SDRAM controller [q]> -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > first upgrade your ise to 7.1.03i latest version, second yes i > tested on > board of memec with Spartan3-1500, i tested on board, and [/q] simulated [q]> too > using a new tb made by me, instantiate generate a clock an put > addr, > data, we and see what you get. > Well to do your interface and test if it working put the DDR > controller > write some addr on memory than read this address, or put a [/q] second [q]> hardware module that could read the memory outside fpga like a > microcontroller and see what you get, a design kit will really [/q] help [q]> in > this time, develop hw without a dev kit is a little .....too [/q] risk, [q]> is > the better words. PLEASE verify your ucf, and verify the [/q] source [q]> code > generated as i said i remember, mig generated defectuous code, > check it > signal by signal instantiation and interconnection by one, [/q] don't [q]> forget > to check all of them first and depurate it. > Anna D. Ashley wrote: > \| Good evening, > \| > \| thank you very much indeed for an answer. > \| > \| I think I should say some more words about my problem. I [/q] have an [q]> ucf > \| file which was provided with my board and in order to map [/q] all [q]> pins > \| correctly I used "Pin editor" of the mig007 tool. > According to "How to > ring > \| use" all red coloured pins are allowed to select for [/q] DQS [q]> from > \| > \| > - -- > Thanks && Regards > LuÃs VitÃ³rio Cargnini > IEEE Member > Mastering @ PUCRS - Electrical Engineer - Microelectronics > Sponsored by CNPQ > Computer Science Bachelor > OpenCores Member <www.opencores.org> > EuropeSwPatentFree [/q] <<A HREF="http://EuropeSwPatentFree.hispalinux.es">http://EuropeSwPatentFree.hispalinux.es</A>> [q]> -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.1 (FreeBSD) > [/q] iD8DBQFC+tDwII4c9KZOcnoRAmV0AJ4jBCDhWsQaFJT7nfM1vRxcehVE4QCg r84m [q]> j89WR136v8IxvknnUPKBXtM= > =XFbt > -----END PGP SIGNATURE----- > > [/q] [/q] Can someone please let me know where the DDR SDRAM controller code is located? I can't find it in the website anymore. Strange, ANy comments on this core's performance comparing to Xilinx Virtex4 ones is appreciated!!! Thanks, Roger ----- Original Message ----- From: xjf77 at yahoo.comxjf77 at y...> To: Date: Fri Aug 26 15:12:38 CEST 2005 Subject: [oc] DDR SDRAM controller Dear Cargnini, I would like to discuss some problems with regards to MIG007. I would like to generate the ddr sdram controller for for ML310 circuit onboard 256MB DIMMs. I have the following problems. 1. MIG007 currently support only unbuffered DDR SDRAM. While my onboard DIMMs is registered, dose this affects the operation? 2. In my case, I am wondering which memory type I can select (component or dimms?). If select DIMMs, then SDRAM part data width is restricted to 64/72 bits. While I see the EDK plb-ddr sdram for ML310 use only 32 bits of DDR SDRAM data pins. How dose it come? Feel puzzled on it. 3. MIG007, as Anna said, seems to be not compatible with the real circuit board pin out constraints, i.e., some real DQS pins are not allowed to be allocated as DQS pin in MIG007-Pin Editor. It's better to neglect the Pin Editor using my own ucf file, I think. Otherwise we have to manually modify the generated ucf file to adapt to the board pin connection. That's it! Thanks a lot in advace. regards, Jeff ----- Original Message ----- From: LuÃs VitÃ³rio Cargnini To: Date: Thu Aug 11 06:15:45 CEST 2005 Subject: [oc] DDR SDRAM controller > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > first upgrade your ise to 7.1.03i latest version, second yes i > tested on > board of memec with Spartan3-1500, i tested on board, and simulated > too > using a new tb made by me, instantiate generate a clock an put > addr, > data, we and see what you get. > Well to do your interface and test if it working put the DDR > controller > write some addr on memory than read this address, or put a second > hardware module that could read the memory outside fpga like a > microcontroller and see what you get, a design kit will really help > in > this time, develop hw without a dev kit is a little .....too risk, > is > the better words. PLEASE verify your ucf, and verify the source > code > generated as i said i remember, mig generated defectuous code, > check it > signal by signal instantiation and interconnection by one, don't > forget > to check all of them first and depurate it. > Anna D. Ashley wrote: > \| Good evening, > \| > \| thank you very much indeed for an answer. > \| > \| I think I should say some more words about my problem. I have an > ucf > \| file which was provided with my board and in order to map all > pins > \| correctly I used "Pin editor" of the mig007 tool. > According to "How to > ring > \| use" all red coloured pins are allowed to select for DQS > from > \| > \| > - -- > Thanks && Regards > LuÃs VitÃ³rio Cargnini > IEEE Member > Mastering @ PUCRS - Electrical Engineer - Microelectronics > Sponsored by CNPQ > Computer Science Bachelor > OpenCores Member > EuropeSwPatentFree http://EuropeSwPatentFree.hispalinux.es> > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.1 (FreeBSD) > iD8DBQFC+tDwII4c9KZOcnoRAmV0AJ4jBCDhWsQaFJT7nfM1vRxcehVE4QCg r84m > j89WR136v8IxvknnUPKBXtM= > =XFbt > -----END PGP SIGNATURE----- > >

DDR SDRAM controller by Unknown on Aug 17, 2006			Not available!
Roger, Just click on the downloads link: <A HREF="http://www.opencores.org/pdownloads.cgi/list/ddr_sdr">http://www.opencores.org/pdownloads.cgi/list/ddr_sdr</A> -Dave ----- Original Message ----- From: rogermao888 at gmail.com<<A HREF="http://www.opencores.org/mailman/listinfo/cores">rogermao888 at g...</A>> To: Date: Tue Aug 15 12:01:19 CEST 2006 Subject: [oc] DDR SDRAM controller [q] Can someone please let me know where the DDR SDRAM controller code is located? I can't find it in the website anymore. Strange, ANy comments on this core's performance comparing to Xilinx Virtex4 ones is appreciated!!! Thanks, Roger ----- Original Message ----- From: xjf77 at yahoo.com<xjf77 at y...> To: Date: Fri Aug 26 15:12:38 CEST 2005 Subject: [oc] DDR SDRAM controller [q]> Dear Cargnini, > I would like to discuss some problems with regards to MIG007. [/q] I [q]> would like to generate the ddr sdram controller for for ML310 > circuit > onboard 256MB DIMMs. I have the following problems. > 1. MIG007 currently support only unbuffered DDR SDRAM. While [/q] my [q]> onboard DIMMs is registered, dose this affects the operation? > 2. In my case, I am wondering which memory type I can select > (component or dimms?). If select DIMMs, then SDRAM part data [/q] width [q]> is > restricted to 64/72 bits. While I see the EDK plb-ddr sdram [/q] for [q]> ML310 > use only 32 bits of DDR SDRAM data pins. How dose it come? [/q] Feel [q]> puzzled on it. > 3. MIG007, as Anna said, seems to be not compatible with the [/q] real [q]> circuit board pin out constraints, i.e., some real DQS pins [/q] are not [q]> allowed to be allocated as DQS pin in MIG007-Pin Editor. It's > better to > neglect the Pin Editor using my own ucf file, I think. [/q] Otherwise we [q]> have > to manually modify the generated ucf file to adapt to the [/q] board pin [q]> connection. > That's it! > Thanks a lot in advace. > regards, > Jeff > ----- Original Message ----- > From: LuÃs VitÃ³rio Cargnini<cargnini at m...> > To: > Date: Thu Aug 11 06:15:45 CEST 2005 > Subject: [oc] DDR SDRAM controller [q] > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > first upgrade your ise to 7.1.03i latest version, second [/q] yes i [q] > tested on > board of memec with Spartan3-1500, i tested on board, and [/q] > simulated [q] > too > using a new tb made by me, instantiate generate a clock [/q] an put [q] > addr, > data, we and see what you get. > Well to do your interface and test if it working put the [/q] DDR [q] > controller > write some addr on memory than read this address, or put [/q] a [q]> second [q] > hardware module that could read the memory outside fpga [/q] like a [q] > microcontroller and see what you get, a design kit will [/q] really [q]> help [q] > in > this time, develop hw without a dev kit is a little [/q] .....too [q]> risk, [q] > is > the better words. PLEASE verify your ucf, and verify the [/q] > source [q] > code > generated as i said i remember, mig generated defectuous [/q] code, [q] > check it > signal by signal instantiation and interconnection by [/q] one, [q]> don't [q] > forget > to check all of them first and depurate it. > Anna D. Ashley wrote: > \| Good evening, > \| > \| thank you very much indeed for an answer. > \| > \| I think I should say some more words about my problem. [/q] I [q]> have an [q] > ucf > \| file which was provided with my board and in order to [/q] map [q]> all [q] > pins > \| correctly I used "Pin editor" of the mig007 [/q] tool. [q] > According to "How to > ring > \| use" all red coloured pins are allowed to select [/q] for [q]> DQS [q] > from > \| > \| > - -- > Thanks && Regards > LuÃs VitÃ³rio Cargnini > IEEE Member > Mastering @ PUCRS - Electrical Engineer - [/q] Microelectronics [q] > Sponsored by CNPQ > > Computer Science Bachelor > OpenCores Member <www.opencores.org> > > [/q] EuropeSwPatentFree > <<A HREF="http://EuropeSwPatentFree.hispalinux.es">http://EuropeSwPatentFree.hispalinux.es</A>> > > -----BEGIN PGP SIGNATURE----- > > Version: GnuPG v1.4.1 (FreeBSD) > > > iD8DBQFC+tDwII4c9KZOcnoRAmV0AJ4jBCDhWsQaFJT7nfM1vRxcehVE4QCg > r84m > > j89WR136v8IxvknnUPKBXtM= > > =XFbt > > -----END PGP SIGNATURE----- > > > > > > [/q] Roger, Just click on the downloads link: http://www.opencores.org/pdownloads.cgi/list/ddr_sdr -Dave ----- Original Message ----- From: rogermao888 at gmail.comrogermao888 at g...> To: Date: Tue Aug 15 12:01:19 CEST 2006 Subject: [oc] DDR SDRAM controller Can someone please let me know where the DDR SDRAM controller code is located? I can't find it in the website anymore. Strange, ANy comments on this core's performance comparing to Xilinx Virtex4 ones is appreciated!!! Thanks, Roger ----- Original Message ----- From: xjf77 at yahoo.com To: Date: Fri Aug 26 15:12:38 CEST 2005 Subject: [oc] DDR SDRAM controller > Dear Cargnini, > I would like to discuss some problems with regards to MIG007. I > would like to generate the ddr sdram controller for for ML310 > circuit > onboard 256MB DIMMs. I have the following problems. > 1. MIG007 currently support only unbuffered DDR SDRAM. While my > onboard DIMMs is registered, dose this affects the operation? > 2. In my case, I am wondering which memory type I can select > (component or dimms?). If select DIMMs, then SDRAM part data width > is > restricted to 64/72 bits. While I see the EDK plb-ddr sdram for > ML310 > use only 32 bits of DDR SDRAM data pins. How dose it come? Feel > puzzled on it. > 3. MIG007, as Anna said, seems to be not compatible with the real > circuit board pin out constraints, i.e., some real DQS pins are not > allowed to be allocated as DQS pin in MIG007-Pin Editor. It's > better to > neglect the Pin Editor using my own ucf file, I think. Otherwise we > have > to manually modify the generated ucf file to adapt to the board pin > connection. > That's it! > Thanks a lot in advace. > regards, > Jeff > ----- Original Message ----- > From: LuÃs VitÃ³rio Cargnini > To: > Date: Thu Aug 11 06:15:45 CEST 2005 > Subject: [oc] DDR SDRAM controller > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > first upgrade your ise to 7.1.03i latest version, second yes i > tested on > board of memec with Spartan3-1500, i tested on board, and > simulated > too > using a new tb made by me, instantiate generate a clock an put > addr, > data, we and see what you get. > Well to do your interface and test if it working put the DDR > controller > write some addr on memory than read this address, or put a > second > hardware module that could read the memory outside fpga like a > microcontroller and see what you get, a design kit will really > help > in > this time, develop hw without a dev kit is a little .....too > risk, > is > the better words. PLEASE verify your ucf, and verify the > source > code > generated as i said i remember, mig generated defectuous code, > check it > signal by signal instantiation and interconnection by one, > don't > forget > to check all of them first and depurate it. > Anna D. Ashley wrote: > \| Good evening, > \| > \| thank you very much indeed for an answer. > \| > \| I think I should say some more words about my problem. I > have an > ucf > \| file which was provided with my board and in order to map > all > pins > \| correctly I used "Pin editor" of the mig007 tool. > According to "How to > ring > \| use" all red coloured pins are allowed to select for > DQS > from > \| > \| > - -- > Thanks && Regards > LuÃs VitÃ³rio Cargnini > IEEE Member > Mastering @ PUCRS - Electrical Engineer - Microelectronics > Sponsored by CNPQ > > Computer Science Bachelor > OpenCores Member > > EuropeSwPatentFree > http://EuropeSwPatentFree.hispalinux.es> > > -----BEGIN PGP SIGNATURE----- > > Version: GnuPG v1.4.1 (FreeBSD) > > > iD8DBQFC+tDwII4c9KZOcnoRAmV0AJ4jBCDhWsQaFJT7nfM1vRxcehVE4QCg > r84m > > j89WR136v8IxvknnUPKBXtM= > > =XFbt > > -----END PGP SIGNATURE----- > > > > > >

DDR SDRAM controller by Unknown on Feb 9, 2007			Not available!
Please i'm looking for a working DDR SDRAM controller; i want to control a dual ranked ddr sdram 64Mx64; i don't know how to configure the opencore controller to get it working. can you help me? ----- Original Message ----- From: Tom at slim.opencores.org<<A HREF="http://www.opencores.org/mailman/listinfo/cores">Tom at s...</A>> To: Date: Thu Jan 19 03:26:44 CET 2006 Subject: [oc] DDR SDRAM controller [q] I recently ripped the ddrsdram controller out of EDK (opbddr_v2_00_b) and got it working. There are a few bugs but they are things I can live with as I intend to use it as a piece of stand-alone IP where I have explicit control of the interface. This version supports bursts of 8. If you are still interested in doing this, send me an email describing the problems you have & I'll try to give you a few tips. ----- Original Message ----- From: Mike Delaney<mmdst23 at g...> To: Date: Sat Dec 17 02:18:22 CET 2005 Subject: [oc] DDR SDRAM controller [q]> I tried it about a year ago, and never did get it to work. [/q] IIRC it [q]> didn't support burst read/writes at the time either, but that [/q] may [q]> have > changed. I ended up trying to rip out the controller from the [/q] EDK [q]> core and wrote an OPB wrapper to talk to it, but that also [/q] didn't [q]> work > on hardware. (This was for a school project, so we gave up on [/q] DDR [q]> at > the end of the semester). > I hope you have much better luck then I did. > Mike > On 12/13/05, jihoon at margi.com <jihoon at margi.com> [/q] wrote: [q] > I did the same thing you are trying to do. > But I think it's too late. > If you have any question, send me an email. > > /Jihoon > > ----- Original Message ----- > From: Anna D. Ashley<ada at c...> > To: > Date: Mon Aug 29 17:19:33 CEST 2005 > Subject: [oc] DDR SDRAM controller > [q]> > Hi all, > > > > meanwhile I had some questions from some of you [/q] about my [q]> problem [q]> > and > > solutions. Unfortunately I have not solved this [/q] problem [q]> and it [q]> > seems to > > be no solution. MIG007 works with a couple of test [/q] boards [q]> supported [q]> > by > > Xilinx and does not work with the rest (or I could [/q] not [q]> find out how [q]> > to > > bring it to work). So I switched to the open cores [/q] DDR [q]> SDRAM [q]> > controller > > design but it is going not so fast because there is [/q] no [q]> any [q]> > help\documentation\support. > > If someone would solve the problem just let me know. > > Also if someone has already used open cores [/q] controller [q]> please tell [q]> > me. > > Best, > > Anna > > xjf77 at opencores.org wrote: [q] > >Hi, Anna, > > I am also working on DDR SDRAM Controller. [/q] Would you [q]> please [q]> > tell me [q] > >if you have solved this problem? If yes, which [/q] tool [q]> did you [q]> > use? MIG007 [q] > >or open core from here? > > Cheers, > >xjf77 > > > >----- Original Message ----- > >From: ada at cwazy.co.uk<ada at c...> > >To: > >Date: Wed Aug 10 12:06:43 CEST 2005 > >Subject: [oc] DDR SDRAM controller > > > > > > [/q] > > > > [/q] > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> > [/q] > > [/q] [/q] Please i'm looking for a working DDR SDRAM controller; i want to control a dual ranked ddr sdram 64Mx64; i don't know how to configure the opencore controller to get it working. can you help me? ----- Original Message ----- From: Tom at slim.opencores.orgTom at s...> To: Date: Thu Jan 19 03:26:44 CET 2006 Subject: [oc] DDR SDRAM controller I recently ripped the ddrsdram controller out of EDK (opbddr_v2_00_b) and got it working. There are a few bugs but they are things I can live with as I intend to use it as a piece of stand-alone IP where I have explicit control of the interface. This version supports bursts of 8. If you are still interested in doing this, send me an email describing the problems you have & I'll try to give you a few tips. ----- Original Message ----- From: Mike Delaney To: Date: Sat Dec 17 02:18:22 CET 2005 Subject: [oc] DDR SDRAM controller > I tried it about a year ago, and never did get it to work. IIRC it > didn't support burst read/writes at the time either, but that may > have > changed. I ended up trying to rip out the controller from the EDK > core and wrote an OPB wrapper to talk to it, but that also didn't > work > on hardware. (This was for a school project, so we gave up on DDR > at > the end of the semester). > I hope you have much better luck then I did. > Mike > On 12/13/05, jihoon at margi.com wrote: > I did the same thing you are trying to do. > But I think it's too late. > If you have any question, send me an email. > > /Jihoon > > ----- Original Message ----- > From: Anna D. Ashley > To: > Date: Mon Aug 29 17:19:33 CEST 2005 > Subject: [oc] DDR SDRAM controller > > > Hi all, > > > > meanwhile I had some questions from some of you about my > problem > > and > > solutions. Unfortunately I have not solved this problem > and it > > seems to > > be no solution. MIG007 works with a couple of test boards > supported > > by > > Xilinx and does not work with the rest (or I could not > find out how > > to > > bring it to work). So I switched to the open cores DDR > SDRAM > > controller > > design but it is going not so fast because there is no > any > > help\documentation\support. > > If someone would solve the problem just let me know. > > Also if someone has already used open cores controller > please tell > > me. > > Best, > > Anna > > xjf77 at opencores.org wrote: > >Hi, Anna, > > I am also working on DDR SDRAM Controller. Would you > please > > tell me > >if you have solved this problem? If yes, which tool > did you > > use? MIG007 > >or open core from here? > > Cheers, > >xjf77 > > > >----- Original Message ----- > >From: ada at cwazy.co.uk > >To: > >Date: Wed Aug 10 12:06:43 CEST 2005 > >Subject: [oc] DDR SDRAM controller > > > > > > > > > > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/cores > > >

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