Hi all!
Curently I am a Master student and I am working on my master thesis.
And for some purposes I have to write or adapt a DDR SDRAM memory
controller (for Xilinx Virtex II board with xc2v4000 FPGA). First I
wanted to adapt DDR SDRAM memory controller from opencores projects
but there is no support and noone ansers questions:( Then I found the
Memory Interface Generator (mig007) tool from Xilinx and generated a
memory interfece. Unfortunatelly I have lots of errors during
translation (in ucf file after I defined all pins acording to my board
ucf file). I asked Xilinx but there is no answer. I do not know what
to do. Could someone help me? I would be glad to have any help.

Best,
Anna

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 first thing i used mig, so i could help you, second is did what you want, Third you will have some problems 8-) The first thing to do with code generated by mig is check all the connections and pin type generated, i remember that mig generate one data-bus signals between buffers and a top interface have a path changed, must bu output and mig generate as input, check all of this first than your code will synthesize. Always when i had problem with mig in 2004 was this the problem, was one signal specifically, unfortunately i forgot what is the signal name 8-( . ada at cwazy.co.uk wrote: | Hi all! | Curently I am a Master student and I am working on my master thesis. | And for some purposes I have to write or adapt a DDR SDRAM memory | controller (for Xilinx Virtex II board with xc2v4000 FPGA). First I | wanted to adapt DDR SDRAM memory controller from opencores projects | but there is no support and noone ansers questions:( Then I found the | Memory Interface Generator (mig007) tool from Xilinx and generated a | memory interfece. Unfortunatelly I have lots of errors during | translation (in ucf file after I defined all pins acording to my board | ucf file). I asked Xilinx but there is no answer. I do not know what | to do. Could someone help me? I would be glad to have any help. | | Best, | Anna | _______________________________________________ | http://www.opencores.org/mailman/listinfo/cores | - -- Thanks && Regards Luís Vitório Cargnini IEEE Member Mastering @ PUCRS - Eletrical Engineer - Microeletronics Sponsored by CNPQ Computer Science Bachelor OpenCores Member EuropeSwPatentFree http://EuropeSwPatentFree.hispalinux.es> -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.1 (FreeBSD) iD8DBQFC+fKvII4c9KZOcnoRAt/WAJ0Y6QNJpW7HYpu3pQAjn6WvWjGYZgCdGkK2 A4toTZG9A2pNPrHjpTBF4MI= =zEB3 -----END PGP SIGNATURE-----

Good evening,

thank you very much indeed for an answer.

I think I should say some more words about my problem. I have an ucf
file which was provided with my board and in order to map all pins
correctly I used "Pin editor" of the mig007 tool. According to "How to
use" all red coloured pins are allowed to select for DQS from
data/strobes list box but we he had to map some DQS to black coloured
pins in order to follow ucf file which was provided with the board (I
think I must follow it for having a working controller). The tool
generated design successfully (after all pins were mapped) but I have
lots of errors during translation (some of them I fixed). All errors are
the same, e.g.

ERROR:NgdBuild:752 - Line 404 in '../par/mem_interface_top.ucf': Could
not find instance(s) 'cntrl0_ddr1_dq(63)' in the design. To suppress
this error, specify the correct instance name or remove the constraint.
The 'Allow Unmatched LOC Constraints' ISE property can also be set (
-aul switch for command line users ).
and here is the line

Line 404: INST "cntrl0_ddr1_dq(63)" LOC = AL32;

I have the same errors (NgdBuild:752) error for all data and strobe
signals. This problem I can not fix. Sure I set all options in ISE GUI
which were described on your web page.

I also have some questions related to your controller. Did you finally
generated a working memory interface with the tool? For which board and
FPGA did you do it? Did you test it with the real board or just simulate
it? The last question is very important for me because I have to test my
design with the board (without simulator) and I do not sure that I could
use ddr_test_bench generated by the tool. Than I have to create my own
interface in order to test the controller but currently I am not quite
sure how to do it.


Thanks.

Best,
Anna

Luís Vitório Cargnini wrote:

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 first upgrade your ise to 7.1.03i latest version, second yes i tested on board of memec with Spartan3-1500, i tested on board, and simulated too using a new tb made by me, instantiate generate a clock an put addr, data, we and see what you get. Well to do your interface and test if it working put the DDR controller write some addr on memory than read this address, or put a second hardware module that could read the memory outside fpga like a microcontroller and see what you get, a design kit will really help in this time, develop hw without a dev kit is a little .....too risk, is the better words. PLEASE verify your ucf, and verify the source code generated as i said i remember, mig generated defectuous code, check it signal by signal instantiation and interconnection by one, don't forget to check all of them first and depurate it. Anna D. Ashley wrote: | Good evening, | | thank you very much indeed for an answer. | | I think I should say some more words about my problem. I have an ucf | file which was provided with my board and in order to map all pins | correctly I used "Pin editor" of the mig007 tool. According to "How to ring | use" all red coloured pins are allowed to select for DQS from | | - -- Thanks && Regards Luís Vitório Cargnini IEEE Member Mastering @ PUCRS - Electrical Engineer - Microelectronics Sponsored by CNPQ Computer Science Bachelor OpenCores Member EuropeSwPatentFree http://EuropeSwPatentFree.hispalinux.es> -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.1 (FreeBSD) iD8DBQFC+tDwII4c9KZOcnoRAmV0AJ4jBCDhWsQaFJT7nfM1vRxcehVE4QCgr84m j89WR136v8IxvknnUPKBXtM= =XFbt -----END PGP SIGNATURE-----

Hi, Can you give more details on the kind of problems that you are facing. Can you cut and past the error messages. We will see and let you know if we could interpret and give some suggestions. - tp ----- Original Message ----- From: ada at cwazy.co.ukada at c...> To: Date: Wed Aug 10 12:06:43 CEST 2005 Subject: [oc] DDR SDRAM controller
projects

Hi, Anna, Have you successfully generated the ddr sdram controller for your circuit board? Regards, jeff ----- Original Message ----- From: ada at cwazy.co.ukada at c...> To: Date: Wed Aug 10 12:06:43 CEST 2005 Subject: [oc] DDR SDRAM controller
projects

Dear Cargnini, I would like to discuss some problems with regards to MIG007. I would like to generate the ddr sdram controller for for ML310 circuit onboard 256MB DIMMs. I have the following problems. 1. MIG007 currently support only unbuffered DDR SDRAM. While my onboard DIMMs is registered, dose this affects the operation? 2. In my case, I am wondering which memory type I can select (component or dimms?). If select DIMMs, then SDRAM part data width is restricted to 64/72 bits. While I see the EDK plb-ddr sdram for ML310 use only 32 bits of DDR SDRAM data pins. How dose it come? Feel puzzled on it. 3. MIG007, as Anna said, seems to be not compatible with the real circuit board pin out constraints, i.e., some real DQS pins are not allowed to be allocated as DQS pin in MIG007-Pin Editor. It's better to neglect the Pin Editor using my own ucf file, I think. Otherwise we have to manually modify the generated ucf file to adapt to the board pin connection. That's it! Thanks a lot in advace. regards, Jeff ----- Original Message ----- From: Luís Vitório Cargninicargnini at m...> To: Date: Thu Aug 11 06:15:45 CEST 2005 Subject: [oc] DDR SDRAM controller
iD8DBQFC+tDwII4c9KZOcnoRAmV0AJ4jBCDhWsQaFJT7nfM1vRxcehVE4QCg
r84m

Hi, Anna, I am also working on DDR SDRAM Controller. Would you please tell me if you have solved this problem? If yes, which tool did you use? MIG007 or open core from here? Cheers, xjf77 ----- Original Message ----- From: ada at cwazy.co.ukada at c...> To: Date: Wed Aug 10 12:06:43 CEST 2005 Subject: [oc] DDR SDRAM controller
projects

Hi all, meanwhile I had some questions from some of you about my problem and solutions. Unfortunately I have not solved this problem and it seems to be no solution. MIG007 works with a couple of test boards supported by Xilinx and does not work with the rest (or I could not find out how to bring it to work). So I switched to the open cores DDR SDRAM controller design but it is going not so fast because there is no any help\documentation\support. If someone would solve the problem just let me know. Also if someone has already used open cores controller please tell me. Best, Anna xjf77 at opencores.org wrote:

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 wow excuse i saw only now this mail i'll read it and answer back in some minutes xjf77 at yahoo.com wrote: | Dear Cargnini, | I would like to discuss some problems with regards to MIG007. I | would like to generate the ddr sdram controller for for ML310 circuit | onboard 256MB DIMMs. I have the following problems. | 1. MIG007 currently support only unbuffered DDR SDRAM. While my | onboard DIMMs is registered, dose this affects the operation? | 2. In my case, I am wondering which memory type I can select | (component or dimms?). If select DIMMs, then SDRAM part data width is | restricted to 64/72 bits. While I see the EDK plb-ddr sdram for ML310 | use only 32 bits of DDR SDRAM data pins. How dose it come? Feel | puzzled on it. | 3. MIG007, as Anna said, seems to be not compatible with the real | circuit board pin out constraints, i.e., some real DQS pins are not | allowed to be allocated as DQS pin in MIG007-Pin Editor. It's better to | neglect the Pin Editor using my own ucf file, I think. Otherwise we have | to manually modify the generated ucf file to adapt to the board pin | connection. | That's it! | Thanks a lot in advace. | regards, | Jeff | | ----- Original Message ----- | From: Luís Vitório Cargninicargnini at m...> | To: | Date: Thu Aug 11 06:15:45 CEST 2005 | Subject: [oc] DDR SDRAM controller | | | _______________________________________________ | http://www.opencores.org/mailman/listinfo/cores - -- Thanks && Regards Luís Vitório Cargnini IEEE Member Mastering @ PUCRS - Electrical Engineer - Microelectronics Sponsored by CNPQ Computer Science Bachelor OpenCores Member EuropeSwPatentFree http://EuropeSwPatentFree.hispalinux.es> -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.1 (FreeBSD) iD8DBQFDE87mII4c9KZOcnoRAs27AJwI8JZIJ1Z4XkxSLd6+DcgtgdrloQCfXxw6 rLdM8XJWvQzeE38ENW+VzXc= =5APc -----END PGP SIGNATURE-----

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 1. yes it make difference i founded this two simple explanations in 2cpu.com, to say in simple form: "first unregistered unbuffered will have better performance There really isn't a lot to say from a technical perspective about unbuffered memory. It's what the vast majority of PCs on the planet use. Essentially, with unbuffered memory the chipset deals directly with the memory itself. There is nothing in between the two parties as they communicate." "Registered modules have additional components (registers) placed between the incoming address and control information and the SDRAM components. These modules are typically used in Servers due to their added reliability (they place much less of an electrical load on the memory controller and therefore make it possible to have as many as 16 or 32 modules in a large system). ~From what I've read, a stick of memory that contains registers will actually hold data for one full clock cycle before it's passed on. A small performance hit is generally incurred as a result. Registered memory is all about scalability and stability." so it make difference in final delay of your application, but you need reliability or performance this is the question 2. oops i don't understood how it happens too, but ..... configuration mig ?, you can't configure the data path width ?? number of banks ? something like this ? (i know that you can), so maybe modifying some parameters could help the generation, other way i don't know what it could be 3. forget the mig pin editor make your own ucf file xjf77 at yahoo.com wrote: | Dear Cargnini, | I would like to discuss some problems with regards to MIG007. I | would like to generate the ddr sdram controller for for ML310 circuit | onboard 256MB DIMMs. I have the following problems. | 1. MIG007 currently support only unbuffered DDR SDRAM. While my | onboard DIMMs is registered, dose this affects the operation? | 2. In my case, I am wondering which memory type I can select | (component or dimms?). If select DIMMs, then SDRAM part data width is | restricted to 64/72 bits. While I see the EDK plb-ddr sdram for ML310 | use only 32 bits of DDR SDRAM data pins. How dose it come? Feel | puzzled on it. | 3. MIG007, as Anna said, seems to be not compatible with the real | circuit board pin out constraints, i.e., some real DQS pins are not | allowed to be allocated as DQS pin in MIG007-Pin Editor. It's better to | neglect the Pin Editor using my own ucf file, I think. Otherwise we have | to manually modify the generated ucf file to adapt to the board pin | connection. | That's it! | Thanks a lot in advace. | regards, | Jeff | | ----- Original Message ----- | From: Luís Vitório Cargninicargnini at m...> | To: | Date: Thu Aug 11 06:15:45 CEST 2005 | Subject: [oc] DDR SDRAM controller | | | _______________________________________________ | http://www.opencores.org/mailman/listinfo/cores - -- Thanks && Regards Luís Vitório Cargnini IEEE Member Mastering @ PUCRS - Electrical Engineer - Microelectronics Sponsored by CNPQ Computer Science Bachelor OpenCores Member EuropeSwPatentFree http://EuropeSwPatentFree.hispalinux.es> -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.1 (FreeBSD) iD8DBQFDE9ToII4c9KZOcnoRAkomAJ4h2bZ0LoQWsHKxuDXbGk2xM0/nAgCfZBe4 bXVnaddQqanflT9tpQCmL7k= =t7d3 -----END PGP SIGNATURE-----

Dear Cargnini, Thanks for your help! Following are my further questions: 1. I can understand there are two kinds of memory flavors, unbuffered and registered. While what I am concerning is, our onboard memory is registered, which is not supported by Mig007. Dose it mean the generated ddr controller will work on my ddr ram? The difference is unbuffered DDR requires 3 differential clock pairs while registered requires only one pair. So what I have done is to find out the other two clock pairs and tried to completely comment them out. There should be no problem in this point because I have not found any other code using the other two clock pairs in the controller. 2. If you can genereate an EDK project with a PLB-DDR controller for ML310 circuit board, you will find the ucf file only uses 32 DDR data pins. What I understand is this is exact requirement of 64bit plb bus interface. Normally the user interface data width is always double the data width of the DDR RAM itself. That's what I am saying in my last email, when I choose the DIMMs memory type, then in the following 'memory Data Width' option, there is only 64/72 bit wide avaiable. This is not so important, I can add all 64bit data pin connection in the ucf file according to the ML310 datasheet. I am just wondering how Xilinx make it, using 32 bit connection with the DDRRAM(which is actually 64bits wide), and we can access the whole memory deepth with this PLB-DDR controller! 3. yes, mig pin editor is not compatible with my circuit board pin out. I can modify the constraint file by myself. Thus it's difficult to add the Logic cell constraints like 'INST "cal_top0/tap_dly0/l26" RLOC=X0Y1;' because that takes rather long time to find out which logic cell is the best choice for each signal. 4. Further question, after I generate the design, I create a new design targets on my device xc2vp30, and copy all the source vhdl code from /rtl directory, while one component/submodule called 'dcmx3y1_2vp30' is always in .edn format, is that for Synplicity? What if I want to synthesis and implement the whole design in XST/ISE. Many thanks for you kind heart! rgds, Jeff --- Luís Vitório Cargnini cargnini at matrix.com.br> wrote:
iD8DBQFDE9ToII4c9KZOcnoRAkomAJ4h2bZ0LoQWsHKxuDXbGk2xM0/nAgCfZBe4
__________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com

I did the same thing you are trying to do. But I think it's too late. If you have any question, send me an email. /Jihoon ----- Original Message ----- From: Anna D. Ashleyada at c...> To: Date: Mon Aug 29 17:19:33 CEST 2005 Subject: [oc] DDR SDRAM controller

I tried it about a year ago, and never did get it to work. IIRC it didn't support burst read/writes at the time either, but that may have changed. I ended up trying to rip out the controller from the EDK core and wrote an OPB wrapper to talk to it, but that also didn't work on hardware. (This was for a school project, so we gave up on DDR at the end of the semester). I hope you have much better luck then I did. Mike On 12/13/05, jihoon at margi.com jihoon at margi.com> wrote:

I recently ripped the ddrsdram controller out of EDK (opbddr_v2_00_b) and got it working. There are a few bugs but they are things I can live with as I intend to use it as a piece of stand-alone IP where I have explicit control of the interface. This version supports bursts of 8. If you are still interested in doing this, send me an email describing the problems you have & I'll try to give you a few tips. ----- Original Message ----- From: Mike Delaneymmdst23 at g...> To: Date: Sat Dec 17 02:18:22 CET 2005 Subject: [oc] DDR SDRAM controller