Hi, Sorry for bother. I am trying to implement the PCI core on a Spartan II 2s200 PCI Board from Memec. Also, I am trying to implement the Simple General PurposeIO core, which is very simple and compatible with Wishbone andcan be downloaded from here: http://www.opencores.com/cvsweb.shtml/simple_gpio/rtl/ I only need output pins. In the header of the simple_gpio.v file says the following (I copy here from there): // Registers: // // 0x00: Control Register // bits 7:0 R/W Input/Output '1' = output mode // '0' = input mode // 0x01: Line Register // bits 7:0 R Status Current GPIO pin level // W Output GPIO pin output level // // Use a pin as an output: // Program the corresponding bit in the control register to 'output mode' ('1'). // Program the GPIO pin's output level by writing to the corresponding bit in the Line Register. // Reading the GPIO pin's Line Register bit while in output mode returns the current output level. My questions are: 1) How can I program the corresponding bit in the control register to 'output mode' ('1')? 2) How can I program the GPIO pin's output level by writing to the corresponding bit in the Line Register? Is that can be done only changing: always @(posedge clk_i or negedge rst_i) if (~rst_i) begin ctrl

Instead of running the usual "if idiot delete" email rule (which I ran on 7 preceding emails), I am actually going to answer. As you said the core is very simple and there isn't anything to add to the 4 lines of explanation. What you're missing is the lack of comprehension of the term register. Perhaps you could try to program the core's registers using a controller. BTW examples of a controller are: a cpu, a fsm (==finite state machine), etc. Cheers, Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of jtrabal at engin.umass.edu Sent: Tuesday, August 16, 2005 5:00 PM To: cores at opencores.org Subject: [oc] GPIO Core Hi, Sorry for bother. I am trying to implement the PCI core on a Spartan II 2s200 PCI Board from Memec. Also, I am trying to implement the Simple General PurposeIO core, which is very simple and compatible with Wishbone andcan be downloaded from here: http://www.opencores.com/cvsweb.shtml/simple_gpio/rtl/ I only need output pins. In the header of the simple_gpio.v file says the following (I copy here from there): // Registers: // // 0x00: Control Register // bits 7:0 R/W Input/Output '1' = output mode // '0' = input mode // 0x01: Line Register // bits 7:0 R Status Current GPIO pin level // W Output GPIO pin output level // // Use a pin as an output: // Program the corresponding bit in the control register to 'output mode' ('1'). // Program the GPIO pin's output level by writing to the corresponding bit in the Line Register. // Reading the GPIO pin's Line Register bit while in output mode returns the current output level. My questions are: 1) How can I program the corresponding bit in the control register to 'output mode' ('1')? 2) How can I program the GPIO pin's output level by writing to the corresponding bit in the Line Register? Is that can be done only changing: always @(posedge clk_i or negedge rst_i) if (~rst_i) begin ctrl http://www.opencores.org/mailman/listinfo/cores