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netlist simulation
by Unknown on Aug 28, 2005 |
Not available! | ||
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look that the module is defined with the same name as it is called.
in u1 it should say:
module u1 ( ... )
endmodule
and in worklib.prioritize:v you should see it called by the same name:
u1 nr2 ( ... )
If it says
u11 nr2 ( ... ) by mistake, it will not find the definition of u11.
----- Original Message -----
From: msaluja at n...
To: cores at o...
Date: Sat, 11 Jan 2003 12:01:07 -0100
Subject: Re: [oc] netlist simulation
----- Original Message -----
From: jae lim jlim0011 at y... >
To: cores at o...
Date: Thu, 18 Jul 2002 14:20:03 -0700 (PDT)
Subject: [oc] netlist simulation
>
> > Hello there > > here is the post synthesis file included in a test > bench. > It is just a small example. But when I use ncverilog > simulate > it, it gave me error saying that : > > Unbounded ncvlog: *W,UNBINS: ?Unbound instance found?: > U1::NR2 in unit worklib.prioritize:v > ........... > > Is there anybody tell me why?? > > Thanks a lot > > Have a nice weekend > > Xia > Hi Looks like , the cell NR2/U1 (module priortize )is being compiled before the vendor specific library file (which should contain the NR2 verilog primitive) is compiled . Does this helps ? -Manit |
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