Please I need your urgent support, related to ACK_I input of Wishbone bus... I ve designed a CPU in vhdl (i am trying to release it with name HPC-16 on OC) supporting only single write and single read bus operations. like any other WB master, it provide slave STB_O and sample the ACK_I on next rising edge. -Since the WB is completely synchronous, should give ACK_I directly to control unit of processor, or pass ACK_I through two stage synchronizer (2 - cascading DFF). i just require fucntional correctness... -suppose if i use synchronizer, and futher suppose for simple configuration I simply connect STB_O of processor to ACK_I. now control unit will recieve the "ack_sync" after two clk periods (in zero-delay simulation exactly on 2nd clk period, in cpu rtl code i donot inserted "after "). just like WB master, control unit after getting ACK_I immediately deassert the STB_O and continue its work (internal operation or next read/write operation) and *donot* wait for "ack_sync" = 0. at this point should control-unit asynchronously reset the synchronizer as well? and/or should control-unit wait until "ack_sync" become 0, for next read/write cycle?