the bus controling issues are creating problems. The complete code of cpu along with documentation is posted on OpenCores.org as *HPC-16* project. cpu only supports single read/write cycles. Currently I just simulating the CPU on modelsim, not tested on cpu. All signal assignments are in zero time, no timing info in CPU RTL or RAM models. i.e no "after unit_time". this is my first cpu...please help //////////////////////////////////////////// --// this code of sync, i tried both archs, --// first one delays the "ack_sync" arrival --// second one donot delay the async arrival entity sync is port ( d : in std_logic; clk : in std_logic; q : out std_logic ); end sync; architecture Behavioral of sync is signal t : std_logic; begin process(clk) begin if rising_edge(CLK) then t RST_I, clk => CLK_I, q => rst_sync ); async : sync port map ( d => ACK_I, clk => CLK_I, q => ack_sync ); --//////////////////////////////////////////////////////// -- combinational predecoding decode: cur_ic ) begin -- defualt assigns to avoid latch SEL_O -- **************************************************** -- ** note: no default assign for "nxt_state" -- ** should i add: "nxt_state -- generate control signals to reset the Program Counter (pc) and FLAGS if rst_sync = '0' then nxt_state -- assign pc contents to memory address reg(connected to address bus): mar -- start instruction fetch cycle SEL_O if ack_sync = '1' then -- ********************************************************* -- -- ** instruction register should be loaded at this point ** -- -- ** otherwise control unit should stay in this state. ** -- -- ** this another reason for adding *sync* to ack_i ** -- -- ** (no need to add wait state circuit for SPARTAN 3 ** -- -- ** BRAMS) ** -- -- ** ?? is this a clean way ?? ** -- -- ********************************************************* -- -- ** any way stop the bus cycle, since we have recieved ** -- -- ** the *ack_sync* ** -- -- ********************************************************* -- -- ** another issue: ** -- -- ** in a "zero delay simulation", if stb_o controls the ** -- -- ** controls the chip-select of RAM, the "cs" of ram ** -- -- ** will be deasserted, resulting in immediate high-z on** -- -- ** data bus, in fact my whole simulation start running ** -- -- ** in delta time, if i remove the sync from ack_i! ** -- -- ********************************************************* -- -- ** note: for any read or write cycle, the cpu ** -- -- ** *does not wait* for ack_sync to become deasserted ** -- -- ** so in simulation, ack_sync generated for fetch2 ** -- -- ** is falsely reused for exec2. ** -- -- ** this would be obvious if use first arch of sync, ** -- -- ** in second arch you will observe a glitch at this ** -- -- ** time. ** -- -- ********************************************************* -- nxt_state -- ** based on current instruction type! ** -- case cur_ic is -- **************************************** -- -- ** several types of instructions, ** -- -- ** please consider *int* and *iret* ** -- -- ** interrupt call and return ** -- -- **************************************** -- -- ** interrupt call: int ** -- -- ** FLAGS and then PC ** -- -- ** are pushed into stack, then PC ** -- -- ** is assigned {vector no. x 8} ** -- -- **************************************** -- -- ** interrupt ret: iret ** -- -- ** memory words are poped into PC and ** -- -- ** then into FLAGS ** -- -- **************************************** -- when ic_int => -- stack pointer is decrmented by two : sp = old sp - 2 -- mar is also assigned with this new value: mar = old sp - 2 -- "mem data reg for output" (mdro) which is connected to data bus -- is assigned zero extended FLAGS: mdro = flags nxt_state -- increament the sp by two: sp = old sp + 2 -- but assign mar old value: mar = old sp nxt_state -- handle invalid instructions by throwing exception -- separate "state chain" to handle the issue nxt_state case cur_ic is ---------------------------------------------- when ic_iret => -- read data word (PC) SEL_O -- assert the tri state control mdro_oe null; -- ***************************************** -- end case; --/////////////////////////////////////// -- ** execution phase 2** -- when exec2 => case cur_ic is when ic_int => if ack_sync = '1' then -- ***************************************** -- ** now we can start another bus cycle: -- ** prepare to push PC -- ***************************************** -- mar = old sp -2 -- sp = old sp - 2 -- mdro = pc nxt_state if ack_sync = '1' then -- **************************************** -- ** mdri might be loaded with mem word, -- ** copy it to pc, prepare for another -- ** pop -- **************************************** -- pc = mdri -- sp = old sp + 2 -- mar = old sp -- nxt_state null; ------------------------------------------- --/////////////////////////////////////// when exec3 => case cur_ic is when ic_int => mdro_oe mdri_ce null; ---------------------------------------------- end case; --/////////////////////////////////////// when exec4 => case cur_ic is ---------------------------------------------- when ic_int => if ack_sync = '1' then -- pc = ext(ir(3..0)) * 8 -- execution complete, poll the interrupt pin nxt_state if ack_sync = '1' then -- flags = mdri -- nxt_state null; ---------------------------------------------- end case; --////////////////////////////////////// -- rest of states --///////////////////////////////////// end case; end process; end rtl; ///////////////////////////////////////////////////////////////////////////////////////////