In FPGA design ,

I have a 16 bit counter and I latch the counter value onto a data bus
and I read the data bus continuously. I make a very fast read out of
the data bus. I have problem here. There is delay in the data bus to
change from one counter value to another counter value. For example
let the counter value be 1403H.I latch it to the data bus. I read the
value. The next counter value will be 1404H. When I latch this data to
the data bus, each data line in the bus takes different time to arrive
at 1404h. For example data line 0 and 1 (0 and 1st Bit should be 0
here). But it takes much time to change state from 1 to 0.Before this
occurs bit 2 become 1.So I read the value 1407h. Can you suggest me
what to do with this transition delay.

Thanks.

That's a natural property of buses; the signals will never transition simultaneously. Whatever is reading those signals should be registered (I assume you mean "registered" when you say "latched") with sufficient time for the signals to settle. In short, you're clearly trying to do something strange here, and you haven't described what it is, and that's most likely the real problem, not that the signals are transitioning perfectly. Perhaps if you describe what you're trying to do with these signals we can help you. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20050924/ed01261f/attachment.htm

IF your design is Globaly Synchronous then this delay should not matter as the values are only read from the bus when the next clock edge changes, typicaly from low to high. ----- Original Message ----- From: powerarm2001 at yahoo.co.inpowerarm2001 at y...> To: Date: Fri Sep 16 19:48:29 CEST 2005 Subject: [oc] Bus delay - FPGA

There is a simple fix for that: you need to pack registers in your
IOBs and this may require adding an extra register level.

I am guessing you are doing something like:

counter_o process (clk)
begin
if (rising_edge(clk)) then
counter_s end if;
end process;

The proper way of doing it for most situations is:

process (clk)
begin
if (rising_edge(clk)) then
counter_s counter_o tool should treat it as a register and pack it in IOBs if the target
device has IOB registers... and all current FPGAs I know of do.
end if;
end process;

The proper way implies that the observable value is always one behind
the register's current value and you have to build the rest of your
design to account for that. Routing inside FPGAs is somewhat slow,
complex and unpredictable. FPGAs are designed for synchronous designs,
they have plenty of D-latches and I recommend that you use them -
particularly the IOB ones since they do not cost you any core logic
and help weed out lots of nonsense in the static timing analysis.