Kindly help with this simulation issue............... in "test2.vhd", the testbench for this simulation contain only ram (ramNx16.vhd) and cpu. (for code and documentation: http://www.opencores.org/projects.cgi/web/hpc-16) i converted the program given below in binary ################################ ## this program test: ## mov, li and hlt instructions ################################ 0:li r0, 5555h 4:mov r1, r0 6:mov sp, r1 8:mov r5, sp 10:hlt ############################## all instructions are executed correctly in simulation... since there is no need for wait states, i'have just connected the the cpu "stb_o" port to cpu "ack_i"... in figure http://www.geocities.com/umairsiddiqui0800/my_pics/hpc-16_sim_problem.jpg consider the signal "/test2/cpu/control/rst_i" "/test2/cpu/control/rst_sync" "/test2/cpu/control/ack_i" "/test2/cpu/control/ack_sync" i'm usng same synchronizer, for both input... but you can see that "ack_sync" is 2 clk late than and "rst_sync" is 1 clk late... also you can see the glich in "ack_sync"... how this thing can be corrected??? please help with this issue...