Hi Robert, hi all, I would like to add the following 2 extensions to the single_port memory model for simulating asynchronous memories: 1. Make the address and data buses unconstrained instead of defining their widths in a package. After that it will be possible to use multiple instances of this model with different address or data port widths within the same design. 2. Trigger it with any change on the data or address buses or on the rnw signal. This is the behaviour real asynchronous memories have. The present model is only triggered on rnw. Reading multiple addresses without a transaction on rnw presently doesn't work. The single_port project is found under Memory core / Single Port ASRAM. Speciality of this model is an efficient use of simulator memory. 1.9GB of memory of my PC are used while I'm simulating my design which contains a model for 512kB of memory. With the LinkedList architecture of the single_port model less than 500MB are used. You can already view the updated documentation at http://www.michaelgeng.de/single_port.html and download the tared and ziped sources with all changes from http://www.michaelgeng.de/vhdl.tar.gz if you want to see them in advance. I would prefer to become maintainer for this project because then I can check in the changes myself. Michael

Hi Michael,

I like your additions and have asked the site admin people to add you as
a maintainer. i'm pleased to know that by using the linked-list
architecture, you were able to cut memory usage by 4x. Did you notice
any change in simulation speed?

regards,

r

On Mon, Oct 10, 2005 at 08:24:07PM +0200, rpaley_yid at yahoo.com wrote:

Thank you for your confidence! I will check in the changes as soon as I have the appropriate
rights.

Before I used your linked list model the simulator required more memory than I have in my PC so
that it started swapping. Because of this in my special case the simulation speed increased even
with the linked list architecture as it doesn't swap any more. I haven't done any exact
measurements neither on memory usage nor on speed, also the 4x increase is a very rough estimation.
I'm just happy that I found a solution to simulate my whole system including external memory.

There's an initial version checked in (1.1) and there's a branch (1.1.1.1). I can't see any
differences. Are there any? What were the reasons for branching?

I can't find any license statements with this core. I would like to see it under the GPL. How do
you think about it?

Michael

On Tue, Oct 11, 2005 at 09:18:43PM +0200, Damjan Lampret wrote:
Robert,

my username at opencores.org is mgeng.

Regards,
Michael

Michael, Please add a GPL copywrite statement in each file and reference the GPL. Also, to avoid problems with links going away, please add a copy of the GPL to this project. The location is.... http://www.gnu.org/copyleft/gpl.txt to the project. regards, r ----- Original Message ----- From: Michael Gengvhdl at M...> To: Date: Tue Oct 11 22:09:32 CEST 2005 Subject: [oc] Extensions to single_port asynchronous memory model

Hi Robert, Damjan, Matjaz, I could successfully add the announced changes. I also added the suggested opencores header and a copy of the LGPL license. Thank you all for your help! Michael On Tue, Oct 11, 2005 at 11:19:26PM +0200, rpaley_yid at yahoo.com wrote: _______________________________________________ http://www.opencores.org/mailman/listinfo/cores