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Small CPU architectures
by Unknown on Oct 17, 2005 |
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I want to do my research on mixed s/n design bcoz i am the person
related to (VLSI)Masters degree holder . I have sufficient knoweledge
to do research or project on mixed s/n design(which includes both
analog and digital).If u r having any offer for that particulars pls
reply sooon
ur's
Msreddy
----- Original Message -----
From: Armando Astarloa jtpascua at b...>
To: cores at o...
Date: Fri, 26 Sep 2003 09:39:51 +0200
Subject: Re: [oc] Small CPU architectures
>
>And, if you *really* want small size, and still want the benefit of
>programmable control, I recommend reading Ken Chapmans nice set
of
>articles about KCPCM - basically what Xilinx calls PicoBlaze:
>
>http://www.xilinx.com/support/techxclusives/techX-home.htm
It is a very good option for Mixed-Core (hard-soft) design. In the Core FFR16 i have embedded two KCPSM and the result in area terms is very good. Armando ----------------------------------------------------------------------------------------------------------------------
Armando Astarloa Cuéllar - Universidad del Pais Vasco UPV/EHU
TecnologÃa Electrónica
Departamento de Electrónica y Telecomunicaciones
Escuela Superior de Ingenieros - Email: jtpascua at b...
Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04
48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59
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Small CPU architectures
by Unknown on Oct 20, 2005 |
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On Mon, 2005-10-17 at 18:37 +0200, maliredyrvr at rediffmail.com wrote:
I want to do my research on mixed s/n design bcoz i am the person
Hmm, you are a "Masters degree holder" ? And you do not know
how to spell "because" and "you" and "are" and "please" ?
And that should be "knowledge" I guess ... Sad, sad sad ...
So I guess your Verilog would look something like:
alws (for always)
asgn (for assign)
cs (for case)
etc, etc, etc
--
rudi
=============================================================
Rudolf Usselmann, ASICS World Services, http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis
****** Certified USB 2.0 HS OTG and HS Device IP Cores ******
related to (VLSI)Masters degree holder . I have sufficient knoweledge to do research or project on mixed s/n design(which includes both analog and digital).If u r having any offer for that particulars pls reply sooon ur's Msreddy |
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Small CPU architectures
by Unknown on Oct 20, 2005 |
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Rudi,
Read closer, they are "related to"... :-) Dalton Rudolf Usselmann wrote:
On Mon, 2005-10-17 at 18:37 +0200, maliredyrvr at rediffmail.com wrote:
I want to do my research on mixed s/n design bcoz i am the person
related to (VLSI)Masters degree holder . I have sufficient knoweledge to do research or project on mixed s/n design(which includes both analog and digital).If u r having any offer for that particulars pls reply sooon ur's Msreddy Hmm, you are a "Masters degree holder" ? And you do not know how to spell "because" and "you" and "are" and "please" ? And that should be "knowledge" I guess ... Sad, sad sad ... So I guess your Verilog would look something like: alws (for always) asgn (for assign) cs (for case) etc, etc, etc |
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