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single_port: replace rnw input by nce, noe and nwe inputs

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single_port: replace rnw input by nce, noe and nwe inputs by Unknown on Nov 5, 2005			Not available!
Hi Robert (or other users interrested to the single_port model), the single_port core presently only has a rnw input signal. That's different to real asynchronous RAMs as you can buy them. They usually have the following signals. nce (not chip enable) noe (not output enable) nwe (not write enable) I think it would be useful to change the interface in this way. The model would then also contain tristate drivers as real RAMs have. In my present design I had to implement these tristate drivers externally. So I could simplify my design by adding the above interface. I think this would also be the case for most other people who want to simulate an external asynchronous RAM. How do you think about it? Michael Hi Robert (or other users interrested to the single_port model), the single_port core presently only has a rnw input signal. That's different to real asynchronous RAMs as you can buy them. They usually have the following signals. nce (not chip enable) noe (not output enable) nwe (not write enable) I think it would be useful to change the interface in this way. The model would then also contain tristate drivers as real RAMs have. In my present design I had to implement these tristate drivers externally. So I could simplify my design by adding the above interface. I think this would also be the case for most other people who want to simulate an external asynchronous RAM. How do you think about it? Michael

single_port: replace rnw input by nce, noe and nwe inputs by markm on Nov 6, 2005			markm Posts: 4 Joined: Jul 24, 2008 Last seen: Sep 23, 2024
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single_port: replace rnw input by nce, noe and nwe inputs by rpaley_yid on Nov 7, 2005			rpaley_yid Posts: 4 Joined: Jan 3, 2003 Last seen: Mar 22, 2018
Hi, I agree. Please update the documentation and timing diagrams. ----- Original Message ----- From: Michael Geng<<A HREF="http://www.opencores.org/mailman/listinfo/cores">vhdl at M...</A>> To: Date: Sat Nov 5 12:06:03 CET 2005 Subject: [oc] single_port: replace rnw input by nce, noe and nwe inputs [q] Hi Robert (or other users interrested to the single_port model), the single_port core presently only has a rnw input signal. That's different to real asynchronous RAMs as you can buy them. They usually have the following signals. nce (not chip enable) noe (not output enable) nwe (not write enable) I think it would be useful to change the interface in this way. The model would then also contain tristate drivers as real RAMs have. In my present design I had to implement these tristate drivers externally. So I could simplify my design by adding the above interface. I think this would also be the case for most other people who want to simulate an external asynchronous RAM. How do you think about it? Michael [/q] Hi, I agree. Please update the documentation and timing diagrams. ----- Original Message ----- From: Michael Gengvhdl at M...> To: Date: Sat Nov 5 12:06:03 CET 2005 Subject: [oc] single_port: replace rnw input by nce, noe and nwe inputs Hi Robert (or other users interrested to the single_port model), the single_port core presently only has a rnw input signal. That's different to real asynchronous RAMs as you can buy them. They usually have the following signals. nce (not chip enable) noe (not output enable) nwe (not write enable) I think it would be useful to change the interface in this way. The model would then also contain tristate drivers as real RAMs have. In my present design I had to implement these tristate drivers externally. So I could simplify my design by adding the above interface. I think this would also be the case for most other people who want to simulate an external asynchronous RAM. How do you think about it? Michael

single_port: replace rnw input by nce, noe and nwe inputs by markm on Nov 8, 2005			markm Posts: 4 Joined: Jul 24, 2008 Last seen: Sep 23, 2024
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