Without extended featutres, as far as I know there are 3 ways to end
the data portion of a transfer. Note: i'm only using 1 master.

(assume WR can be replaced with RD)

1) Write the WR and STO bits in the command register.
- 8 bits will be written, an Ack/Nack will follow from the slave,
master then issues stop signal

2) Write the WR bit in the command register (expecting repeated start)
- 8 bits will be written, an Ack/Nack will follow from the slave, and
then a repeated start signal command will start a new transaction.

3) Write the WR bit in the command register....then seperately write
the STO bit in the command register.
- *should* work as in case 1, but it doesnt for me.

Case 3 fails for me because, when a Stop command is issued by itself
to the command register, the 'tip' flag is not set. So, there isnt a
flag that can be polled to prevent the next instruction from being
issued prematuerly.

So in my case the next transaction starts prematurely (before the stop
signal is properly completed) and the start signal never properly
appears, and thus my slave will not leave the idle state.