Dear Wishbone experts, I have read the wishbone b.3 specs. I would like to ask a few questions. 1. In RULE 3.25 (page 40) it says: "[CYC_O] MUST be negated no earlier than the rising [CLK_I] edge that qualifies the negation of [STB_O]". But, in the 3.2.1 SINGLE READ Cycle (page 47), in the CLOCK EDGE 0, I read: "MASTER asserts [CYC_O] and [TGC_O()] to indicate the start of the cycle. MASTER asserts [STB_O] to indicate the start of the phase". And here comes my questions. If CYC_O MUST be negated "after (no earlier than)" the rising [CLK_I] edge that qualifies the negation of [STB_O] then, why are negated STB_O and CYC_O at the same time in the wishbone timings?. shouldn't be negated STB_O first and CYC_O in the next clock cycle?. What am I forgetting?. Thanks a lot and best regards, mimoto __________________________________ Yahoo! Mail - PC Magazine Editors' Choice 2005 http://mail.yahoo.com